Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (crolles 2) Sas

International Business Machines Corporation

Stmicroelectronics S.a.

Francois Andrieu

Remy Berthelon

Perrine Batude

Maud Vinet

Yannick Le Tiec

Simeon Morvan

Pierre Morin

Shay Reboh

Didier Dutartre

Lamine Benaissa

Bastien Giraud

Sylvain Maitrejean

Jean-Charles Barbe

Raluca Tiron

Olivier Weber

Denis Rideau

Sebastien Barnola

Emmanuel Josse

Sonarith Chhun

Nicolas Degors

Dominique Golanski

Laurent Brunet

Gregory Bidal

Jerome Belledent

Pierre Perreau

Jerome Mazurier

Elise Baylac

Victor Boureau

A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.

Method of fabricating a semiconductor substrate having a stressed semiconductor region

A production of a device with superimposed levels of components including in this order providing on a given level Nprovided with one or more components produced at least partially in a first semiconductor layer: a stack including a second semiconductor layer capable of receiving at least one transistor channel of level N, above said given level N, the stack including a ground plane layer situated between the first and second semiconductor layers as well as an insulator layer separating the ground plane layer from the second semiconductor layer, one or more islands being defined in the second semiconductor layer. A gate is formed on at least one island. Distinct portions are etched in the second semiconductor ground plane layer. An isolation zone is formed around the island by the gate and the island.

3D circuit provided with mesa isolation for the ground plane zone

Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

Assembly for 3D circuit with superposed transistor levels

A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer

Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

Integrated circuit chip with strained NMOS and PMOS transistors

The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

3D SRAM circuit with double gate transistors with improved layout

An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

3D circuit transistors with flipped gate

An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.

Integrated circuit comprising balanced cells at the active

An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Integrated circuit including balanced cells limiting an active area

Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

Method of forming strained MOS transistors

An integrated circuit comprising: first to third nMOS transistors with different threshold voltages, and first to third pMOS transistors with different threshold voltages, the nMOS transistors having channel regions made of silicon subjected to tensile stress and/or said pMOS transistors having channel regions made of SiGe subjected to compressive stress; a first well and a second well that are arranged underneath the nMOS transistors and underneath the pMOS transistors, respectively, with one and the same doping; two nMOS gate stacks comprising one and the same material, two of the nMOS gate stacks comprising materials having separate work functions, an nMOS gate stack having one and the same material as a pMOS gate stack, with the equation: Gp*Vdds&#x2212;Gn*Gnds=Sn*|&#x3c3;n|+Sp*(|&#x3c3;p|&#x2212;1.65*10)&#x2212;VarCais+K.

Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes

A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Method of manufacturing a device with MOS transistors

A substrate is successively provided with a support (), an electrically insulating layer (), and a semi-conductor material layer (). A first protective mask () completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask () partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask () so as to form a third etching mask. The semi-conductor material layer () is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask () protecting the second area (B).

Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors

There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon&#x2014;germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon&#x2014;germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

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Grenoble, France

Francois Andrieu