Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

National University of Singapore

Micron Technology Incorporated

Francis Lionel Benistant

Shesh Mani Pandey

Yanxiang Liu

Benjamin Colombeau

Jianwei Peng

Peijie Feng

Lap Chan

Purakh Raj Verma

Mei Sheng Zhou

Liang Choo Hsia

Yisuo Li

Yun Ling Tan

Baofu Zhu

Sai Hooi Yeong

Bangun Indajang

Pei Zhao

Kun Liu

Debora Chyiu Hyia Poon

Elgin Kiok Quek

Alex See

Paul J Rudeck

Shao-fu Sanford Chu

Kelly T Hurley

Shiang Yang Ong

Zhao Lun

El Mehdi Bazizi

Ming Li

Alex K H See

Namchil Mun

Zhiqing Li

Bhagawan Sahu

Hong Yang

Deepanjan Datta

Kim Hyun Sik

Xiaoping Wang

Li Cao

Gang Chen

One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

Device with diffusion blocking layer in source/drain region

A system and method for simulating behavior of a spin transfer torque magnetic random access memory (STT-MRAM) device includes a hardware processor (HP) and logic instructions (LI) stored in memory. The LI are executed by the HP to configure a library of functional blocks (FBs) to capture physical phenomenon of at least one element of the STT-MRAM configured in the form of a magnetic stack. Selected elements of the stack are mapped into a set of selected FBs (SFBs). The mapping converts the stack to a spin device circuit (SDC) represented by the SFBs. The SFBs are assembled to form the SDC replicating the stack. The SDC includes an electron spin transport, a magnet-dynamics, a magnetic coupling and a coupled electron transport+magnet-dynamics FBs. A set of output parameters simulating the STT-MRAM is generated by the SFBs in response to receiving a set of input parameters.

System and method for modular simulation of spin transfer torque magnetic random access memory devices

A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.

Multiple-step epitaxial growth S/D regions for NMOS FinFET

A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.

Devices and methods for forming a device are disclosed. A transistor is formed on the substrate. The transistor includes a gate, a source and a drain. An insulation layer is formed on the substrate. The insulation layer is partially disposed on the gate and a sidewall of the gate. The drain is offset from the gate by the insulation layer. An overlayer is formed on the substrate covering the transistor and insulation layer. A field plate in the form of a field plate contact is formed in the overlayer. The field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.

Extended drain metal-oxide-semiconductor transistor

Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

Isolation scheme for high voltage device

A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

FinFET conformal junction and high epi surface dopant concentration method and device

A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

FinFET conformal junction and abrupt junction with reduced damage method and device

FinFET conformal junction and high EPI surface dopant concentration method and device

An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.

Integrated circuit system with double doped drain transistor

Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.

Semiconductor devices and methods of forming the semiconductor devices including a retrograde well

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Method for fabricating semiconductor devices with reduced junction diffusion

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Singapore, Singapore

Francis Lionel Benistant