International Business Machines Corporation

Francis Joseph Downes, Jr

John Steven Kresge

Robert Maynard Japp

Jaynal Abedin Molla

Gerald Walter Jones

Raymond Thomas Galasco

Voya Rista Markovich

Anthony P Ingraham

Mark Vincent Pierson

David Brian Stone

Donald Seton Farquhar

Luis Jesus Matienzo

David James Alcoe

James Robert Wilcox

Elizabeth F Foster

Robert David Sebesta

Stephen Joseph Fuerniss

Ronald A Kaschak

Gary Ray Hill

Daniel C Van Hart

Cheryl L Tytran-Palomaki

Gerald G Advocate, Jr

Anilkumar Chinuprasad Bhatt

Robert Lee Lewis

Robert D Topa

Lawrence P Lehman

Joseph Edward Varsik

John Frank Surowka

Oscar A Moreno

Cindy M Reidsema

A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Integrated circuit structure

A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

Method of making a multi-layered interconnect structure

An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a substrate having a metallic sheet within a dielectric layer. The metallic sheet includes a metal such as copper. An opening in the substrate, such as a blind via, is formed by laser drilling through the dielectric layer and partially through the metallic sheet. If the opening is a blind via, then the laser drilling is within an outer ring of the blind via cross section using a laser beam having a target diameter between about 20% and about 150% of a radius of the blind via cross section. A surface at the bottom of the opening, called a &ldquo;blind surface,&rdquo; includes a metallic protrusion formed by the laser drilling, such that the metallic protrusion is integral with a portion of the blind surface. The metallic protrusion includes the metal of the metallic sheet and at least one constituent element from the dielectric layer. The metallic protrusion is then etched to form a metallic interlocking structure that is integral with the portion of the blind surface. The metallic interlocking structure includes discrete metallic fibers, with each metallic fiber having a curved (or curled) geometry. Each metallic fiber has its own unique composition that includes the metal, at least one constituent element of the dielectric layer, or both.

Formation of a metallic interlocking structure

An arrangement and method for the degassing small high-aspect ratio drilled holes or vias which are present in panels such as printed circuit boards prior to wet chemical processing, including copper plating of the vias, in order to remove any air or gas bubbles from the vias tending to inhibit the reliable plating thereof. This is carried out through the utilization of an ultrasonic prewetting in a liquid bath preceding cleaning for the electroless plating process, thereby enabling all of the vias or holes to be degassed; in effect, having air removed and the vias or holes filled with liquid; thereby allowing subsequent process cleansing solutions to easily flow into the respective holes or vias in order to facilitate the electroless copper plating process.

Arrangement and method for degassing small-high aspect ratio drilled holes prior to wet chemical processing

A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.

Blind via formation in a photoimageable dielectric material

A structure that adhesively couples a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is on a top surface of the chip. A temporary or permanent stiffener of ferrous material is on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. After the solder bump has been reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure, the solder bump is reconfigured. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. After the chip and carrier are cooled, the C4 solder structure is adhesively and conductively coupled to the pad.

Chip C4 assembly improvement using magnetic force and adhesive

An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

Electronic package with high density interconnect layer

Metallic interlocking structure

An electroplating apparatus provides high current electrical connections in a small area to a workpiece. The contact area may use a dendrite surface to improve the connection. An insulative gasket prevents electroplating fluids from entering the region about the contact area. A heavy core laminated within a supporting structure provides uniform current distribution of high electrical currents to the dendrite covered contact areas.

Laminated electroplating rack and connection system for optimized plating

According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface. The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Method of planarizing a curved substrate and resulting structure

A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. The solder bump is reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure. The reflowing reconfigures the solder bump. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. The chip and carrier are cooled, resulting in the C4 solder structure being adhesively and conductively coupled to the pad.

The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The method comprises the following steps: providing a substrate having circuitry disposed thereon; applying a photoresist to the substrate at a thickness which is preferably about the height of the intended dendrite height; imaging the photoresist to expose all or a portion of the top surface of the circuitry; forming the dendrites; and removing the photoresist. The photoresist which is employed to control the dendrite height is applied so that the photoresist either: abuts the edge of the circuitry leaving the top surface of the circuitry exposed; or abuts the edge of the circuitry and extend over the top edge of the circuitry so that a portion of the top surface of the circuitry is exposed; or does not touch the circuitry nor an area surrounding the base of the circuitry. The method of the present invention provides uniform dendrites, that is, the dendrites along the edge of the circuitry are within about 50%, preferably about 40%, more preferably within about 25% of the average dendrite height; preferably the dendrites along the edge of the circuitry are within 10% of the highest non-edge dendrite. The invention also relates to electronic structures having uniform dendrites disposed thereon.

Method for uniform plating of dendrites

An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.

Growing community of inventors

Vestal, NY, United States of America

Francis Joseph Downes, Jr