International Business Machines Corporation

Francesco Preda

Lloyd Andre Walls

Daniel Douriet

Brian Leslie Singletary

Charles Leon Arvin

Jean Audet

Anson Jay Call

Brian W Quinlan

Charles L Reynolds

Paul Robert Walling

Daniel Mark Dreps

Stefano Sergio Oggioni

Wiren Dale Becker

Nam Huu Pham

David James Alcoe

Sungjun Chun

Jose A Hejase

Ronald P Nowak

Junyan Tang

Pavel Roy Paladhi

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Dense via pitch interconnect to increase wiring density

A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Thin film capacitors for core and adjacent build up layers

Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

Semiconductor package metal shadowing checks

A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to 'jog' circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Fabrication method for circuit substrate having post-fed die side power supply connections

A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Continuously referencing signals over multiple layers in laminate packages

Circuit substrate having post-fed die side power supply connections

An electronic device carrier () adapted for transmitting high-frequency signals, including a circuitized substrate with a plurality of conductive layers (to) insulated from each other, the conductive layers being arranged in a sequence from a first one of the conductive layers () wherein a plurality of signal tracks () each one ending with a contact area () for transmitting a high-frequency signal are formed, and a reference structure () connectable to a reference voltage or ground for shielding the signal tracks the reference structure includes at least one reference track () formed in a second one of the conductive layers () adjacent to the first conductive layer and at least one further reference track formed in one of the conductive layers () different from the first and second conductive layer, a portion of each signal track excluding at least the area corresponding to the orthographic projection of associated contact area being superimposed in plan view to a corresponding reference track and at least a part of the area corresponding to the orthographic projection of the contact area associated to each signal track being superimposed in plan view to a corresponding further reference track with interposition of a floating conductive track, i.e. a track not connected to any signal, reference voltage or ground track.

Electronic device carrier adapted for transmitting high frequency signals

Growing community of inventors

New Braunfels, TX, United States of America

Francesco Preda