Adesto Technologies Corporation

Micron Technology Incorporated

Axon Technologies Corporation

Adesto Technologies France Sarl

Foroozan Sarah Koushan

Deepak Kamalanathan

Tomoko Ogura Iwasaki

Ji-Hye Gale Shin

Juan Pablo Saenz Echeverry

Jayasree Nayar

Michael Allen Van Buskirk

Venkatesh P Gopinath

Wei Ti Lee

Shane Charles Hollmer

John Dinh

John Ross Jameson

John Ross Jameson, Iii

Shinji Sato

Michael N Kozicki

Yi Ma

Christina Papagianni

John Sanchez

Antonio R Gallo

David Kim

Janet Wang

Jeffrey Allan Shields

Mark D Kellam

Chakravarthy Gopalan

Derric Lewis

Philippe Blanchard

Derric Jawaher Herman Lewis

Vasudevan Gopalakrishnan

A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

Managing pre-programming of a memory device for a reflow process

Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

Memory devices including heaters

Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.

Multi-stage erase operation for a memory device

A first write operation is performed to write a first portion of a set of host data to a first location of a memory device. It is determined whether a first elapsed time since the first operation is performed does not satisfy a time condition. Responsive to determining that the first elapsed time does not satisfy the time condition, a second write operation is performed to write a second portion of the set of host data to a second location of the memory device not adjacent to the first location.

Write operations to mitigate write disturb

An integrated circuit device can include a plurality of nonvolatile memory elements having values that vary randomly or pseudo-randomly from one another; a selection circuit configured to select a plurality of nonvolatile memory elements that vary randomly or pseudo-randomly in response to a received challenge value; and sense circuits configured to generate a response value based on the values of the selected nonvolatile memory elements. Related methods and systems are also disclosed.

Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values

A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.

A request to write a set of host data is received. A first plurality of write operations is performed to write a first portion of the set of host data to a first set of memory cells of the memory device arranged in a first pattern. The first set of memory cells arranged in the first pattern comprises alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells. A second plurality of write operations is performed to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern. The second set of memory cells arranged in the second pattern comprises other alternating memory cells on each word line of the memory device adjacent to the first set of memory cells.

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof

In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Resistive memory device with ramp-up/ramp-down program/erase pulse

A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields.

Nonvolatile memory elements having conductive structures with semimetals and/or semiconductors

In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Resistive devices and methods of operation thereof

In accordance with an embodiment of the present invention, a memory cell includes a two terminal access device disposed above a semiconductor substrate. The access device includes a two terminal resistive switching device having substantially zero retention. The two terminal resistive switching device has a low resistance state and a high resistance state. A memory device is disposed above the semiconductor substrate. The memory device is coupled to the access device.

Two terminal resistive access devices and methods of formation thereof

A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.

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San Jose, CA, United States of America

Foroozan Sarah Koushan