Agilent Technologies, Inc.

National Semiconductor Corporation

Fidel Muradali

Neal C Jaarsma

Robert Campbell Aitken

Chinsong Sul

John Stephen Walther

Garrett O'Brien

Ismed D S Hartano

Joan Figueras

In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is applied to a predefined number of sites subsequent to the first defective site. If the more stringent test sequence does not identify a second defective site in the predefined number of sites subsequent to the first defective site, then the default test sequence is resumed.

Adaptive test time reduction for wafer-level testing

A method is provided for dynamically increasing or decreasing the amount of test data that is applied to die locations on a wafer under test. As on-wafer locations are traversed and tested, the amount of test stimuli applied to subsequent locations is adjusted. This adjustment is based upon the results of previously tested locations. The effect is that the test program detects regions of the wafer that are more likely to fail and applies more complete testing to these areas. Other areas of the wafer may receive reduced testing. By automatically adapting the test mix to suit the potential failure patterns, wafer testing time is reduced.

The present disclosure describes a technique for debugging an integrated circuit having a parallel scan-chain architecture. Blocking circuits are introduced at the inputs and/or outputs of scan-chain branches. The blocking circuits allow the inputs to and/or the outputs from the scan-chain branches to be selectively blocked. This allows individual scan-chain branches to be isolated and debugged.

Technique for debugging an integrated circuit having a parallel scan-chain architecture

A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.

Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits

Monitor circuitry for identifying an operational status of a device under test (DUT) includes a comparison circuit and a sense amplifier. The comparison circuit comprises a set of control transistors and a set of sense transistors. The control transistors include control input terminals for receiving reference signals to establish a testing condition with respect to a signal relationship between a first current flow and a second current flow. The sense transistors are operatively associated with the control transistors, such that biasing the sense input terminals of the sense transistors with sampled signals received from the DUT varies the signal relationship between the first current flow and the second current flow. The variation in the signal relationship is accelerated by the sense amplifier. The variation in the signal relationship is indicative of the operational status of the DUT at the sampling instance for acquiring the sampled signals.

Monitor circuitry and method for testing analog and/or mixed signal integrated circuits

Scan path structures are provided for integrated circuits which contain one or more cores or levels of sub-cores embedded within the cores. Circuitry is provided to permit scan testing of scan elements, such as scan wrapper cells and scan chains, in the cores and sub-cores by providing scan paths which share access to limited numbers of scan test ports of the integrated circuit under test. This solves the problem of having sufficient scan ports at the integrated circuit boundaries for the increasingly higher number of scan paths which require access to these scan ports.

Integrated circuit with scan test structure

An integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors accessible from the chip input and output terminals, respectively. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus. The scan-out enable circuit connects the output terminal of the first scan-chain to an output terminal associated with the core module. The access word determines the connections and the operations carried out by the core module in the test mode. The access registers of the core modules are connected together to form an access scan-chain having an input terminal accessible from one of the chip input terminals. One of the core modules has an output terminal connected to the second conductor of the test data bus. Core modules may also include other scan-chains used in the testing hardware. In such modules, the scan-in enable and scan-out enable circuits include circuitry for selecting the scan-chain connections to the test data bus and the output terminal of the core module.

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Mountain View, CA, United States of America

Fidel Muradali