Micron Technology Incorporated

Micron Semiconductor, Inc.

Other

Fernando N Gonzalez

Roger R Lee

Chandra V Mouli

Trung Tri Doan

Raymond A Turi

Graham Richard Wolstenholme

Tyler A Lowrey

D Mark Durcan

Guy T Blalock

Er-Xuan Ping

Randhir P Thakur

Mike P Violette

Jeffrey W Honeycutt

David Y Kao

Gurtej S Sandhu

Kirk D Prall

Ruojia R Lee

J Brett Rolfson

John T Moore

Michael P Violette

Tim J Corbett

Raymond P Scholer

Charles L Ingalls

John K Zahurak

Russell C Zahorik

Kevin L Beaman

David L Chapek

Terry Gafron

Ron Weimer

Parag Banerjee

Howard E Rhodes

Luan C Tran

Pierre C Fazan

Randhir P S Thakur

Ronald Allen Weimer

Ardavan Niroomand

Robert B Kerr

Joseph J Karniewicz

David F Cheffings

Francis L Benistant

W Richard Barbour

Francis L Bensistant

Charles H Dennison

Kunal R Parekh

Gordon A Haller

Thomas Arthur Figura

Don Carl Powell

Steven T Harshfield

Randal W Chance

Willard L Hofer

Lyle Jones

Angus C Fox, Iii

M Ceredig Roberts

Donwon Park

Alan Mondada

Yauh-Ching Liu

Sergei V Koveshnikov

Fawad Ahmed

Annette L Martin

J Dennis Keller

John Zhang

Larry D Cromar

Ray Turi

Ranshir P S Thakur

Randir P Thakur

A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Apparatus including a capacitor-less memory cell and related methods

This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

Transistor structures and integrated circuitry comprising an array of transistor structures

A multi-dimensional solid state lighting (SSL) device array system and method are disclosed. An SSL device includes a support, a pillar having several sloped facets mounted to the support, and a flexible substrate pressed against the pillar. The substrate can carry a plurality of solid state emitters (SSEs) facing in various directions corresponding to the sloped facets of the pillar. The flexible substrate can be a flat substrate prepared using planar mounting techniques, such as wirebonding techniques, before bending the substrate against the pillar.

Multi-dimensional solid state lighting device array system and associated methods and structures

A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Capacitor-less memory cell, device, system and method of making same

A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

Localized biasing for silicon on insulator structures

A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines

Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Method of manufacturing devices having vertical junction edge

A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

Method for programming a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell

The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure

Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ('bottom electrodes') of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Container capacitor structure and method of formation thereof

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Boise, ID, United States of America

Fernando N Gonzalez