Micron Technology Incorporated

Fernando Gonz&aacute;lez

Howard E Rhodes

Luan C Tran

D Mark Durcan

Robert B Kerr

David F Cheffings

The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures. Following implantation and formation of the gettering structures, thermal processing may be carried out in order to induce lateral spread or widening of each of the gettering structures. In some embodiments, it may be desirable that each gettering structure substantially contact an adjacent gettering structure, which may be accomplished by directional ion implantation. In another embodiment of the present invention, a dual implantation is carried out. The shallow implantation migrates during thermal processing to fill crystal originated particles or pits (COPs) within the semiconductive substrate.

Fabrication of semiconductor gettering structures by ion implantation

An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory device. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Floating gate isolation device

Semiconductor gettering structures

A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Growing community of inventors

Boise, ID, United States of America

Fernando González

Growing community of inventors

Boise, ID, United States of America

Fernando Gonz&aacute;lez

Fernando González