Nxp Usa, Inc.

Freescale Semiconductor,inc.

Fernando A Santos

Lakshminarayan Viswanathan

Audel Sanchez

Jaynal Abedin Molla

Margaret A Szymanowski

Mahesh K Shah

Jerry Lynn White

Sarmad K Musa

Li Li

Scott Duncan Marshall

Yun Wei

Zhiwei Gong

Boon Yew Low

Hussain Hasanali Ladhani

David F Abdo

Colby Greg Rampley

Lakshmi Narayan Ramanathan

Fui Yee Lim

Mohd Salimin Sahludin

Jeffrey Kevin Jones

Burton Jesse Carpenter

Lan Chu Tan

Elie A Maalouf

Basim H Noori

Lu Li

Ricardo Uscola

L Mali Mahalingam

Eduard Jan Pabst

Dominic (PohMeng) Koey

Taek Kyu Kim

Li Ll

Lu Ll

Audel A Sanchez

A circuit module includes a module substrate with a mounting surface, and a plurality of conductive features and electronic circuitry coupled to the mounting surface. Encapsulant material covers the electronic circuitry and the mounting surface, and an upper surface of the encapsulant material defined a first surface of the circuit module. A plurality of leadframe terminals, each separated from a non-planar leadframe unit, extend from the conductive features at the mounting surface through the encapsulant material toward the first surface of the circuit module. Each of the leadframe terminals is formed from an elongated planar conductive feature of a leadframe unit, and the plurality of leadframe terminals is electrically coupled to the electronic circuitry through the conductive features and the module substrate. Encapsulant divots may extend into the encapsulant material from the first surface of the circuit module, and proximal ends of the leadframe terminals terminate at the encapsulant divots.

Circuit modules with encapsulant-embedded leadframe terminals, and methods of fabricating such circuit modules

A device includes a package body including a central flange and an amplifier module mounted to the central flange of the surface-mount device. The amplifier module includes a module substrate mounted to the central flange. The module substrate includes a first die mount window, a first circuitry on a first surface of the module substrate, a second circuitry on the first surface of the module substrate, and a first amplifier die mounted on the central flange. The first amplifier die is at least partially disposed within the first die mount window and the first amplifier die is electrically connected to the first circuitry and the second circuitry. The first circuitry is electrically connected to a first lead of the package body and the second circuitry is electrically connected to a second lead of the package body.

Surface-mount amplifier devices

Radio frequency (RF) packages containing multilevel power substrates and associated fabrication methods are disclosed. In an embodiment, the method includes producing a multilevel substrate panel by obtaining a base panel level containing prefabricated base structures and having a surface through which metallic surfaces of the prefabricated base structures are exposed. A secondary panel level is formed on the base layer to include patterned metal features embedded in a secondary dielectric body and electrically contacting the exposed metallic surfaces of the prefabricated base structures at a direct plated interface. The presingulated array of multilevel power substrates is separated into singulated multilevel power substrates each including a base substrate level formed from a singulated piece of the base panel level and a secondary substrate level formed from a singulated piece of the secondary substrate level.

Radio frequency packages containing multilevel power substrates and associated fabrication methods

Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.

Leadless power amplifier packages including topside termination interposer arrangements and methods for the fabrication thereof

Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Methods of fabricating leadless power amplifier packages including topside terminations

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Circuit modules with front-side interposer terminals and through-module thermal dissipation structures

A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

Packaged dies with metal outer layers extending from die back sides toward die front sides

Leadless power amplifier packages including topside terminations and methods for the fabrication thereof

An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Packaged electronic devices with top terminations

Method of wafer dicing for wafers with backside metallization and packaged dies

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Semiconductor package having an isolation wall to reduce electromagnetic coupling

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

Molded air cavity packages and methods for the production thereof

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.

Methods of manufacturing packaged electronic devices with top terminations

Growing community of inventors

Chandler, AZ, United States of America

Fernando A Santos