Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Inc.

Intel Corporation

Other

Numonyx B.v.

Unisersita′ Degli Studi Di Pavia

Stmicroelectronics N.v.

Universitá Degli Studi Di Pavia

Ferdinando Bedeschi

Umberto Di Vincenzo

Riccardo Muzzetto

Claudio Resta

Roberto Gastaldi

Fabio Pellizzer

Efrem Bolandrina

Richard Edward Fackenthal

Enzo M Donze

Ward D Parkinson

Giulio Casagrande

Meenatchi Jagasivamani

Marco Ferraro

Innocenzo Tortorelli

Christophe Vincent Antoine Laurent

Andrea Martinelli

Durai Vishak Nirmal Ramaswamy

Kirk D Prall

Huy Thanh Vo

Alessandro Calderoni

Suryanarayana B Tatapudi

Ravi Annavajjhala

Corrado Villa

Roberto Bez

Tyler A Lowrey

Guido Torelli

Hyun Yoo Lee

Osama Khouri

Michele Maria Venturini

Claudia Palattella

Daniele Vimercati

Graziano Mirichigni

Michele Piccardi

Paolo Fantini

Angelo Visconti

Nevil N Gajera

Ravi Prakash Gutala

Hari Giduturi

Stefan Frederik Schippers

Adam Saleh El-Mansouri

Jeffrey Edward Koelling

Hyunyoo Lee

Ruili Zhang

Alessandro Cabrini

Paolo Amato

Karthik Sarpatwari

Augusto Benvenuti

Paola Zuliani

Pierguido Garofalo

Johnny Javanifard

Christian Caillat

Yen Chun Lee

Francesco Mastroianni

Andrea Ghetti

Rich Fackenthal

Loris Vendrame

Giorgio Bosisio

Anthony Suk Ko

Meenatchi Jagasivmani

Patrick Wu

Enzo Michele Donzè

Andrea Fantini

Christian Marc Benoit Caillat

Gutala Ravi

Anthony Ko

Enzo Donze'

Rich E Fackenthal

Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.

Counter-based sense amplifier method for memory cells

A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.

Counter-based methods and systems for accessing memory cells

Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.

Memory array seasoning

A detection circuit may be configured to receive an input signal indicative of a data state and to detect the data state using charge sharing between two capacitors to achieve detection with threshold compensation. The detection circuit may include semi-latch circuitry and boosting circuitry to expedite the detection, thereby achieving high speed at low power consumption and low circuit size.

Threshold compensated detector for memory sense

Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

Transistor configurations for vertical memory arrays

Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.

Cascoded sense amplifiers for self-selecting memory

Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

Parallel access in a memory array

Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

Performing sense operations in memory

Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

Shared decoder architecture for three-dimensional memory arrays

Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

Single plate configuration and memory array operation

A system includes a memory array having pattern cells and data cells. The pattern cells are configured to store only a first logic state. The data cells are configured to store the first logic state or a second logic state. Bias circuitry is configured to apply voltages to the pattern cells and data cells. Sensing circuitry is configured to read the pattern cells. A controller is configured to apply, using the bias circuitry, first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh a codeword; and apply, using the bias circuitry, the refresh of the codeword.

Refresh determination using memory cell patterns

Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

Read operations based on a dynamic reference

Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

Signal drop compensated memory

Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

Multiple transistor architecture for three-dimensional memory arrays

Systems and methods for reading a first and second plurality of memory cells include applying a first ramping voltage with a first increment for each ramping step to read the first plurality of cells, counting, among the first plurality of cells at each ramping step, a first number of logic 1 cells, comparing the first number with a threshold at each ramping step of the first ramping voltage, determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the threshold for the first time, applying a second voltage lower than the first voltage to read the second plurality of cells, and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment lower than the first predetermined increment for each ramping step to read the second plurality of cells.

Forward looking algorithm for vertical integrated cross-point array memory

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Biassono, Italy

Ferdinando Bedeschi