Intel Corporation

Feras Eid

Johanna M Swan

Adel A Elsherbini

Aleksandar Aleksov

Georgios C Dogiamis

Sasha N Oster

Shawna M Liff

Telesphor Kamgaing

Thomas L Sounart

Valluri Ramana Rao

Henning Braunisch

Krishna Bharath

Veronica Aleman Strong

Weng Hong Teh

Vijay K Nair

Qing Ma

Mathew J Manusharow

Baris Bicen

Kevin Lai Lin

Robert L Sankman

William J Lambert

Yidnekachew S Mekonnen

Omkar G Karhade

Kimin Jun

Amit S Baxi

Vincent S Mageshkumar

Sarah Kay Haney

Stephen L Morein

Nitin A Deshpande

Javier Soto Gonzalez

Brandon M Rawlings

Christopher J Nelson

Mohammad Enamul Kabir

Javier Soto

Zhichao Zhang

Kyu Oh Lee

Chandra Mohan Jha

Suddhasattwa Nad

Sergio Antonio Chan Arguedas

Meizi Jiao

Jessica Gullbrand

Melissa A Cowan

Han Wui Then

Kemal Aygun

John Stephen Guzek

Ravindranath Vithal Mahajan

Islam A Salama

Gerald S Pasdast

Joe F Walczyk

Braxton L Lathrop

Charles A Gealer

John J Beatty

Beomseok Choi

Nadine L Dabby

Kristof Darmawikarta

Zhiguo Qian

Mihir K Roy

Yoshihiro Tomita

Je-Young Chang

Ashish Gupta

Sandeep B Sane

Julien Sebot

Paul J Diglio

Weihua Tang

Kevin P O'brien

Kumar Ranganathan

Wen-Ling Huang

Tyler N Osborn

Don W Nelson

Ian A Young

Van H Le

Sujit Sharan

Chia-Pin Chiu

Min Suet Lim

Eng Huat Goh

Randy B Osborne

Kaladhar Radhakrishnan

James Chris Matayabas, Jr

Ravi V Mahajan

Jiun Hann Sir

Pramod Malatkar

Edvin Cetegen

David Johnston

Xavier Francois Brun

Rachael Jade Parker

Shankar Devasenathipathy

Kelly P Lofgreen

Kyle Yazzie

Chytra Pawashe

Joseph B Petrini

Nader N Abazarnia

Arnab Sarkar

Zhihua Li

Tannaz Harirchian

Akhilesh P Rallabandi

Qiang Yu

Ahmed Abou-Alfotouh

Arghya Sain

Shawna M Lift

Prasanna Raghavan

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Cooling of conformal power delivery structures

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Hybrid backside thermal structures for enhanced ic packages

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets

Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries

Technologies for high throughput additive manufacturing for integrated circuit components

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Electronics package device technology is disclosed. In one example, an electronics package device () comprises substrate () supporting an electronics component () and an interconnect via (-) electrically coupled to the electronics component such that at least a portion of the electronics component is disposed between the interconnect via and the substrate. The interconnect via can be directly coupled to the electronics component such that the interconnect via and the electronics component are vertically disposed between a second electronics package device () and the substrate. A second electronics package device can be stacked to the first electronics package device, and can comprise similar architecture of the interconnect via attached to the electronics component as with the first electronics package. Thus, 3D package size is significantly reduced. Associated systems and processes are disclosed.

Architectures and methods of fabricating 3D stacked packages

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Liquid cooled interposer for integrated circuit stack

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

Capacitors and resistors at direct bonding interfaces in microelectronic assemblies

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Thermal management in integrated circuit packages

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

Modular microchannel thermal solutions for integrated circuit devices

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

High-throughput additively manufactured power delivery vias and traces

Growing community of inventors

Chandler, AZ, United States of America

Feras Eid