International Business Machines Corporation

Tokyo Electron Limited

Globalfoundries Inc.

Fenton Read McFeely

John Jacob Yurkas

Chih-Chao Yang

Sandra Guy Malhotra

Vijay Narayanan

Alessandro Cesare Callegari

Kevin K Chan

Paul Michael Solomon

Eduard Albert Cartier

Sufi Zafar

Yumiko Kawano

Gert J Leusink

Dianne L Lacey

Cyril Cabral, Jr

Paul Charles Jamison

Hideaki Yamasaki

Douglas Andrew Buchanan

Michael Abramovich Gribelyuk

Kenneth Parker Rodbell

Andrew Herbert Simon

Gerrit J Leusink

Kenji Suzuki

Christopher Peter D'Emic

Robert Rosenberg

Supratik Guha

Conal Eugene Murray

Rajarao Jammy

Matthew Warren Copel

Tatsuo Hatano

Panayotis Constantinou Andricacos

Michael Wayne Lane

Atsushi Gomi

Tsukasa Matsuda

Emmanuel P Guidotti

Kazuhito Nakamura

Daniel C Edelstein

Evgeni Petrovich Gousev

Deborah A Neumayer

Hon-Sum Philip Wong

Kathryn Wilder Guarini

Stephan Alan Cohen

Patrick Ronald Varekamp

Erin C Jones

Alessandro Curioni

Ismail C Noyan

Huiling Shang

Masahito Sugiura

Pushkar Ranade

Hyungjun Kim

Milan Paunovic

Steven H Boettcher

Wanda Andreoni

Lijuan Huang

Douglas A Buchanan

Carlo A Pignedoli

Cevdet Ismail Noyan

John J Yourkas

Guy M Cohen

Ramachandra Divakaruni

Arne Watson Ballantine

Christian Lavoie

Hariklia Deligianni

Katherine Lynn Saenger

Alejandro Gabriel Schrott

Martin Michael Frank

Stephen Mark Rossnagel

Richard Alan Haight

James Bowler Hannon

Joseph Francis Shepard, Jr

Chao-Kun Hu

Masamichi Hara

Cory Wajda

Harald F Okorn-Schmidt

Mitsuhiro Tachibana

Ferenc Miklos Bozso

Satoshi Oida

Wilma Jean Horkans

Peter Stevens Locke

Ricky S Amos

Keith Thomas Kwietniak

Joseph S Newbury

Philippe Mark Vereecken

Theodore Harold Zabel

Daisuke Kuroiwa

Paul F Seidler

Jennifer L Gardner

Mark M Holl

Steven P Kowalczyk

Robert R Young, Jr

Enrico Mosca

Evengi Gousev

Joseph P Shepard, Jr

Koumei Matsuzava

Kyle Erik Litz

Mark Monroe Banaszak Holl

Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

Method and structure to improve the conductivity of narrow copper filled vias

Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

Method to fabricate copper wiring structures and structures formed thereby

A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.

Structure and process for metallization in high aspect ratio features

Techniques for forming narrow copper filled vias having improved conductivity

An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

Noble metal cap for interconnect structures

A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge), antimony (Sb) and nitrogen (N) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of nitrogen-doped GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400&#xb0; C., which makes the inventive method compatible with existing interconnect processes and materials. In some embodiments, the inventive method is a non-selective CVD process, which means that the nitrogen-doped GeSb materials are deposited equally well on insulating and non-insulating materials. In other embodiments, a selective CVD process is provided in which the nitrogen-doped GeSb materials are deposited only on regions of a substrate in a metal which is capable of forming an eutectic alloy with germanium.

Chemical vapor deposition method for the incorporation of nitrogen into materials including germanium and antimony

A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.

Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation

The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

Improved high aspect ratio vias and techniques for the formation thereof are provided. In one aspect, a method of fabricating a copper plated high aspect ratio via is provided. The method comprises the following steps. A high aspect ratio via is etched in a dielectric layer. A diffusion barrier layer is deposited into the high aspect ratio via and over one or more surfaces of the dielectric layer. A copper layer is deposited over the diffusion barrier layer. A ruthenium layer is deposited over the copper layer. The high aspect ratio via is filled with copper plated onto the ruthenium layer. A copper plated high aspect ratio via formed by this method is also provided.

Structure to facilitate plating into high aspect ratio vias

A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.

Method for improving the selectivity of a CVD process

A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO, AlOand other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000&#xb0; C. A low temperature/low pressure CVD technique with Re(CO)as the source material is used when Re is to be deposited.

High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

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