Silicon Storage Technology, Inc.

Freescale Semiconductor,inc.

Huawei Technologies Co., Limited

University of California

Vivo Mobile Communication Co., Ltd.

South China University of Technology

Hon Hai Precision Industry Co., Ltd.

Hewlett Packard Enterprise Development LP

Hong-fu Jin Precision Industry (shenzhen) Co., Ltd.

Future Wei Technologies, Inc.

Semiconductor Manufacturing International (shanghai) Corporation

Agency for Science, Technology and Research

Semiconductor Manufacturing International (beijing) Corporation

Los Alamos National Security, LLC

Huazhong University of Science and Technology

Feng Zhou

Nhan Do

Xian Liu

Jinho Kim

Chien-Sheng Su

Catherine Decobert

Serguei Jourba

Hieu Van Tran

Cheong Min Hong

Ko-Min Chang

Jeng-Wei Yang

Steven Lemke

Frank Kelsey Baker, Jr

Parviz Ghazavi

Thuan Vu

Anh Ly

Yi Zhang

Stanley Hong

Chunming Wang

Zhixian Chen

Peter J Kuhn

Yongyong Zheng

Xin Meng

John P Nolan

Hua Jin

Meihua Huang

Yanjun Lu

Jixiang Gao

Zhengwu Peng

Haibo Sun

Jietao Dai

Liejun Li

Hung Quoc Nguyen

Yu Meng Li

Jin Wang

Wei Wang

Mark Reiten

Dan Zhang

Hui Calvin Yang

Hua-Dong Cheng

Miao Zhang

Chun-Ming Chen

Prateep Tuntasood

Wen-Chuan Lian

Wei Min Wang

Man-Tang Wu

Srinivasa D Murthy

Hao Deng

Zhiyong Li

Robert Henry Kraus, Jr

Guoqing Zhang

Chung-Kuan Cheng

Lin Ye

Xiaojun Yang

Hailong Yu

Xinpeng Wang

Hongyu Chen

Jianhua Xu

Zhen Xu

Lujun Zhang

Ning Jiang

Santosh Hariharan

Jianyu Liu

Tiejun Liu

Xiaodong Shang

Yingchun Chen

Qiaozhen Li

Junfeng Ge

Ruijuan Wang

Lijuan Feng

Bo Yao

Meiyan Zhang

Ronald Graham

Esther Y Cheng

Yaxin Wu

Jiao He

Wang Xinpeng

Quanfeng Zhang

Guo-Qiang Lo

Degao Li

Haixin Huang

Chunyan Song

Qi Tan

A method for manufacturing thin-specification high-Ti wear-resistant steel NM450 comprises the steps of preparing melted iron in a blast-furnace, preprocessing the melted iron, smelting the melted iron in a converter, refining the melted steel in a LF furnace, refining the melted steel in a RH furnace, conventional slab continuous casting, heating the slab in a heating furnace, dephosphorizing the slab by high-pressure water, heating the slab in a hot continuous rolling mill, performing ultra fast cooling, reeling, flattening, heating, quenching, tempering and finishing.

Method for manufacturing thin-specification high-Ti wear-resistant steel NM450

A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).

Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps

Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

Set-while-verify circuit and reset-while verify circuit for resistive random access memory cells

An information processing method and a terminal are provided. The terminal has a first screen and a second screen, and the method includes: in a case that running interfaces of applications are separately displayed on the first screen and the second screen, if a target event is received, displaying, on a target screen, a floating control that is used to indicate the target event; receiving an input for the floating control; and processing the target event in response to the input for the floating control, where the target screen is the first screen or the second screen.

Information processing method and terminal

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

Method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices

A thin gauge wear-resistant steel sheet, including the following chemical elements expressed in percentage by weight: 0.15-0.20 wt. % of carbon; 1.2-1.8 wt. % of manganese; 0.1-0.40 wt. % of copper; 0.15-0.30 wt. % of molybdenum; 0.20-0.40 wt. % of chromium; 0.03-0.06 wt. % of niobium; 0.01-0.03 wt. % of titanium; 0.0006-0.0015 wt. % boron; less than 0.015 wt. % of phosphorus; less than 0.010 wt. % of sulphur; and the balance being ferrum and unavoidable impurities, wherein the thickness of the steel sheet is in a range of 3.0 to 8 mm.

Thin gauge wear-resistant steel sheet and method of manufacturing the same

Disclosed are a light module and a mobile terminal. The light module includes: a support body, substrate, and light-transmitting element. The support body has a light path channel. The substrate is connected to the support body, is located at one end of the light path channel, and has a light source located in the light path channel. The light-transmitting element is connected to the support body, to seal an opening at the other end of the light path channel. A side face of the light-transmitting element that faces the light source has first and second electrical contact points, and a photosensitive coating capable of converting light energy into electrical energy; the first and second electrical contact points are electrically connected by the photosensitive coating, and are configured to connect to a detection module, so that the detection module detects a voltage across the first and second electrical contact points.

Light module and mobile terminal

Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling

A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices

A channel latency determining method, a positioning method, and device, the method including obtaining, by a communications device, device location information of a calibration user equipment (UE), calculating a propagation delay according to the device location information and prestored location information of an antenna, where the propagation delay is a time between transmitting a radio signal by the calibration UE and receiving the radio signal by the antenna, calculating a time of arrival according to the radio signal transmitted by the calibration UE to the antenna, where the time of arrival is a time obtained through calculation according to a time of arrival (TOA) estimation algorithm, and determining a channel latency according to the propagation delay and the time of arrival, where the channel latency is positively correlated with the time of arrival and is negatively correlated with the propagation delay.

Channel latency determining method, positioning method, and related device

Embodiments provide a positioning method, an assistant site, and a system, to improve positioning accuracy of a mobile terminal. The method according to the embodiments of the present invention includes: generating, by an assistant site, a downlink assisted positioning signal; and sending, by the assistant site, the downlink assisted positioning signal to a mobile terminal. The downlink assisted positioning signal can enable a base station to determine position information of the mobile terminal based on a measurement result obtained by the mobile terminal by measuring the downlink assisted positioning signal.

Positioning method, assistant site, and system

A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.

Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same

A method for genetic transformation of edible mushrooms is provided relating to the technical field of genetic transformation of, enoki mushroom and shiitake. The disclosed method for genetic transformation ofincludes: inoculatingliquid mycelia into a foxtail-millet-grain culture medium, and pre-culturing them at 20-25&#xb0; C. untilmycelia grow on surfaces of foxtail millet grains. This method uses the foxtail millet grains as an attachment matrix, and during the pre-culturing and co-culturing, the culture substrate is shaken up every day. The method for genetic transformation of enoki mushroom or shiitake includes: inoculation of enoki mushroom mycelia or shiitake mycelia, activated culturing of, andinfecting a foxtail millet grain-enoki mushroom mycelium matrix or a foxtail millet grain-shiitake mycelium matrix.

Method for genetic transformation of edible mushrooms

A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

Split gate non-volatile memory cells and logic devices with FINFET  structure, and method of making same

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Fremont, CA, United States of America

Feng Zhou