Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

University of California

National Taiwan University

Feng Wei Kuo

Chewn-Pu Jou

Huan-Neng Chen

Lan-Chou Cho

William Wu Shen

Wen-Shiang Liao

Robert Bogdan Staszewski

Yen-Jen Chen

Kuang-Kai Yen

Shuo-Mao Chen

Chen-Hua Douglas Yu

Chih-Hang Tung

Jui-Feng Kuan

Hui Yu Lee

Hung-Chih Lin

Ho-Hsiang Chen

Hao Chen

Ching-Nen Peng

Ming-Chieh Liu

Lee Tsung Hsiung

Yi-Kan Cheng

Jack Liu

Tze-Chiang Huang

Shyh-An Chi

Tsung-Hsiung Lee

Chin-Yuan Huang

Seyednaser Pourmousavian

Kai-Yun Lin

Min-Jer Wang

Yun-Han Lee

Ying-Ta Lu

Hsien-Yuan Liao

Jia-Liang Chen

Der-Chyang Yeh

Mei-Show Chen

I-Ting Lee

Simon Yi-Hung Chen

Chuei-Tang Wang

Hsiao-Tsung Yen

Fu-Lung Hsueh

Tsung-Hsien Tsai

Mill-Jer Wang

Chin-Wei Kuo

Yu-Ling Lin

Shen-Iuan Liu

Ching-Shun Yang

Jinn-Yeh Chien

Ching-Hui Chen

Masoud Babaie

Yanghyo Kim

Tsung-Hsiung Li

You-Jen Wang

Willaim Wu Shen

Kuang Kai Yen

Kyle Yen

A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Integrated circuit stack verification method and system for performing the same

An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Photonics integrated circuit package

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Systems and methods for shielded inductive devices

Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Integrated fan-out package with 3D magnetic core inductor

An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.

Optical device and method of manufacturing the same

An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Integrated circuit with radio frequency interconnect

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits

Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Multiband QAM interface for slab waveguide

A device includes a scattering structure and a collection structure. The scattering structure is arranged to concurrently scatter incident electromagnetic radiation along a first scattering axis and along a second scattering axis. The first scattering axis and the second scattering axis are non-orthogonal. The collection structure includes a first input port aligned with the first scattering axis and a second input port aligned with the second scattering axis. A method includes scattering electromagnetic radiation along a first scattering axis to create first scattered electromagnetic radiation and along a second scattering axis to create second scattered electromagnetic radiation. The first scattering axis and the second scattering axis are non-orthogonal. The first scattered electromagnetic radiation is detected to yield first detected radiation and the second scattered electromagnetic radiation is detected to yield second detected radiation. The first detected radiation is phase aligned with the second detected radiation.

Polarization independent optoelectronic device and method

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

Growing community of inventors

Zhudong, Taiwan

Feng Wei Kuo