Siliconware Precision Industries Co., Ltd.

Feng-Lung Chien

Yi-Hsin Chen

Yi-Hung Lin

Ke-Chuan Yang

Chao-Dung Suo

Chih-Shun Chen

Shih-Kuang Chiu

Chun-Chi Ke

Randy H Y Lo

Meng-Tsung Lee

Jui-Meng Jao

Sui-An Kao

Randy Hy Lo

Po-Hao Yuan

Chun-Sheng Ho

Chun-chi Ke

Huang-Chuan Chang

A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.

Semiconductor structure and fabrication method thereof

A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art.

Conductive bump structure on substrate and fabrication method thereof

A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

Semiconductor device and fabrication method thereof

A process for forming a lead-free bump on an electronic component includes preparing the electronic component with at least one bond pad and a passivation layer formed thereon; forming an under bump metallurgy (UBM) structure on the passivation layer and the bond pad; applying a photoresist over the passivation layer, the photoresist having at least one opening corresponding to the bond pad; depositing a thick copper layer (about 1 to 10 &#x3bc;m thick) in the opening by electroplating; applying a copper-free or low-copper-content solder material on the copper layer; and performing a reflowing procedure under a suitable reflow temperature profile to allow copper ions to diffuse from the copper layer to the solder material so as to form the lead-free bump. This increases the copper content in the solder material but not raising the reflow temperature profile, thereby preventing deterioration of the photoresist due to over heat.

Process for forming lead-free bump on electronic component

A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP. However, since no aluminum layer is included in the metallization structure, a Cu/NiV specific etchant would only etch away the copper layer and the nickel-vanadium layer but not the aluminum-based PBP, thus leaving the unmasked portion of the aluminum-based PBP intact.

Circuit probing contact pad formed on a bond pad in a flip chip package

A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer

A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.

Growing community of inventors

Taichung, Taiwan

Feng-Lung Chien