Winbond Electronics Corporation

Feng-Jung Chang

Tzu-Ming Ou Yang

Chang-Hung Lin

Shih-Han Hung

A semiconductor structure including a substrate, buried word line structures, a transistor structure, a first hard mask layer, hard mask marks, a second hard mask layer, and contacts. The substrate includes a first region and a second region. The buried word line structures are located in the substrate in the first region. The transistor structure is located on the substrate in the second region. The first hard mask layer is located on the transistor structure. The first hard mask layer has recesses. The hard mask marks are located in the recesses. The second hard mask layer is located on the substrate in the first region. The second hard mask layer has openings. The contacts are located in the openings.

Semiconductor structure and manufacturing method thereof

Provided is a DRAM including: a substrate, a plurality of chop structures, and a plurality of buried word lines. The plurality of chop structures are located in the substrate. Each of the plurality of chop structures comprises a first portion and a second portion. The first portion is located above the second portion, and a width of the second portion is less than a width of the first portion. The plurality of buried word lines, located at bottoms of a plurality of buried word line trenches. The plurality of buried word line trenches passes through the first portion of the plurality of chop structures and the substrate.

Dynamic random access memory having word line buried in chop structure with different widths

A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer, a first work function layer, a barrier layer, and a second work function layer. The gate dielectric layer is formed on the sidewalls and the bottom surface of a trench. The work function layer is formed in the trench and contacts the sidewalls and the bottom surface of the gate dielectric layer. The barrier layer is formed on the top surface of the first work function layer. The second work function layer is formed on the barrier layer, and the sidewall of the second work function layer is separated from the gate dielectric layer by a distance. The semiconductor structure further includes an insulating layer in the trench and on the second work function layer.

Semiconductor structure having buried gate structure and method of manufacturing the same

Provided is a method of manufacturing a DRAM. A plurality of openings are formed in the substrate. A hard mask is formed on the sidewall of an upper part of each opening. The substrate and the hard mask are partially removed to form a plurality of isolation trenches and to define active regions. Each active region is located between the isolation trenches and remaining portions of the hard mask are located on two sides of each active region. The isolation trenches and the openings are filled with a dielectric layer. The substrate and the dielectric layer are partially removed to form a plurality of buried word line trenches. Each buried word line trench extends along a third direction and passes through the active regions, the openings and the isolation trenches. A plurality of buried word lines are formed in the buried word line trenches.

Dynamic random access memory and method of manufacturing the same

A dynamic random access memory (DRAM) and a method of fabricating the same are provided. The DRAM includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The plurality of first isolation structures are located in the substrate to define a plurality of active areas arranged along a first direction, wherein the plurality of active areas and the plurality of first isolation structures are alternately arranged along the first direction. The plurality of word line structures pass through the plurality of active areas and the plurality of first isolation structures. The plurality of word line structures are arranged along a second direction and extended along a third direction. The plurality of second isolation structures are located in the substrate where the plurality of word line structures are interleaved with the plurality of active areas and located between the two adjacent first isolation structures. The plurality of third isolation structures cover the plurality of word line structures.

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Taichung, Taiwan

Feng-Jung Chang