Taiwan Semiconductor Manufacturing Comp. Ltd.

Feng-Inn Wu

Sheng-Chen Wang

Jung-Yu Li

Shu-Bin Hsu

Ren-Guei Lin

Yu-Chen Wei

Hsiu-Ming Yeh

Huang-Jen Hsu

Chih-Hung Tsai

Jheng-Si Su

Tzi-Yi Shieh

Yuan-Hsuan Chen

Kuang-Hung Lin

Hui-Ting Tsai

Tzuyi Hsieh

Kung-Ming Liu

Tzuyi Shieh

Jia-Jhen Chen

Te-Chia Hsu

In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.

Method of manufacturing a semiconductor device and a semiconductor device

The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.

CMP safe alignment mark

A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

Polishing head, chemical-mechanical polishing system and method for polishing substrate

A method includes supplying slurry onto a polishing pad. A wafer is held against the polishing pad with a first piezoelectric layer interposed between a pressure unit and the wafer. A first voltage generated by the first piezoelectric layer is detected. The wafer is pressed, using the pressure unit, against the polishing pad according to the detected first voltage generated by the first piezoelectric layer. The wafer is polished using the polishing pad.

A polishing head includes a carrier head and a plurality of pressure units arranged on the carrier head. At least two of the pressure units are located on the same circumferential line relative to a center axis of the carrier head.

A method of using a chemical mechanical polishing (CMP)apparatus that includes a apparatus is provided. The method includes providing a conditioning disc for conditioning the polishing pad, where the conditioning disc includes a plurality of portions of subsystem discs. The portions may be regions of the disc that are concentric. Each portion of the disc is operable to rotate at a different angular velocity. In some embodiments, a different applied loading is provided to each of the portions of the disc in addition to or in lieu of the different angular velocities.

Method of CMP pad conditioning

A semiconductor manufacturing method includes several operations. One operation is catching an image of a predetermined location on a surface of a pad installed in a chemical mechanical polishing (CMP) apparatus by a surface detector. One operation is transferring the image of the predetermined location to a processor. One operation is calculating a surface roughness value of the predetermined location from the image. One operation is comparing the surface roughness value with a threshold value by the processor to determine if the surface roughness condition at the predetermined location is smaller than the threshold value, and the surface is configured for polishing a to-be-polished surface of a wafer.

Semiconductor manufacturing apparatus and method thereof

A chemical mechanical polishing apparatus includes a platen, a polishing head, a magnetizable polishing pad, and an electromagnetic component. The magnetizable polishing pad is disposed between the polishing head and the platen. The electromagnetic component is configured for fastening the magnetizable polishing pad on the platen.

Chemical mechanical polishing apparatus and polishing method using the same

To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This localized planarization, which is often carried out in a localized planarization station downstream of a CMP station, applies localized planarization to less than the entire face of the wafer to correct localized non-planar features. Other systems and methods are also disclosed.

Localized CMP to improve wafer planarization

A chemical mechanical polishing (CMP) apparatus is provided that includes a conditioning disc for conditioning a polishing pad of the CMP apparatus. The conditioning disc includes a plurality of portions of subsystem discs. The portions may be regions of the disc that are concentric. Each portion of the disc is operable to rotate at a different angular velocity. In some embodiments, a different applied loading is provided to each of the portions of the disc in addition to or in lieu of the different angular velocities.

Apparatus for CMP pad conditioning

The present disclosure relates to a slurry distribution system having a distribution tube connected between a mixing tank and a CMP tool. The mixing tank is configured to generate a polishing mixture comprising a diluted slurry having abrasive particles that enable mechanical polishing of a workpiece. The polishing mixture is transported between the mixing tank and a CMP tool by way of a transport piping. An energy source, in communication with the transport piping, transfers energy to the abrasive particles within the polishing mixture, thereby preventing accumulation of the abrasive particles within the transport piping.

Slurry supply system for CMP process

A system includes a chuck with a retaining ring on a first surface thereof. The first surface and the retaining ring are both circular, the retaining ring having a first inner circumference. The system also includes a platen with a second surface, and the second surface faces the first surface and is operable to move with the first surface. The system further includes an air zone circumscribed by the first inner circumference that provides an effective inner circumference different from the first inner circumference.

Systems providing an air zone for a chucking stage

At the conclusion of chemical mechanical polishing (CMP) there is found to be a topography difference at the periphery of the wafer. For example, for a 200 mm wafer, the oxide surface in a peripheral region up to 20 mm wide, may end up about 1,000 &angst; above or below the central portion of the surface. This problem has been overcome by varying the type of polishing pad and retainer ring from one CMP operation to the next. Thus, if the equipment that is used to effect a given CMP step results in a post CMP surface in which the periphery of the wafer is higher than the center, CMP equipment for the next layer is selected that, operating alone, would result in a surface in which the periphery of the wafer is lower than the center. The two CMP operations thus cancel each other and a uniformly flat final surface results. The conditions required to produce either surface topography are described and discussed.

Growing community of inventors

Taichung, Taiwan

Feng-Inn Wu