Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Feng Han

Shuai Zhang

Jian Wu

Lianjie Li

YanBin Lu

Shui Liang Chen

Jian-Hua Lu

Zhong-Hao Chen

Lian-Jie Li

Lu Zhang

Shengtian Lu

Chenglin Zhang

LinChun Gui

An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

LDMOS with enhanced safe operating area and method of manufacture

A PIN diode detector includes a substrate. The PIN diode detector further includes a plurality of PIN diode wells in a pixel region, wherein each of the plurality of PIN diode wells has a first dopant type. The PIN diode detector further includes a connecting ring well and a plurality of floating ring wells in a peripheral region, wherein the connecting ring well and plurality of floating ring wells have the first dopant type. The PIN diode detector further includes a field stop ring well surrounding the plurality of floating ring wells, wherein the field stop ring well has a second dopant type opposite the first dopant type. The PIN diode detector further includes a blanket doped region. The blanket doped region extends continuously through an entirety of the pixel region and an entirety of the peripheral region, and the blanket doped region has the second dopant type.

Pin diode detector, method of making the same, and system including the same

An integrated circuit includes a substrate and a semiconductor material layer over the substrate. The integrated circuit includes a first source structure in the semiconductor material layer. The first source structure includes a first doped well. The integrated circuit includes a drain structure in the semiconductor material layer. The drain structure includes a second doped well. The integrated circuit includes a second source structure in the semiconductor material layer. The second source structure includes a third doped well. The drain structure is between the first source structure and the second source structure. The integrated circuit includes a first deep trench isolation (DTI) extending through the first doped well; and a first thermal contact extending through the first DTI. The thermal contact is in direct contact with the substrate. The first DTI is between the thermal contact and the first doped well.

Semiconductor device having a thermal contact and method of making

A method of making an integrated circuit includes operations related to forming an oxide layer over a top surface of a substrate; depositing a layer of semiconductor material over the oxide layer; and manufacturing a thermal substrate contact extending through the layer of semiconductor material and the oxide layer to the top surface of the substrate. The thermal substrate contact is against, but does not extend through, the substrate. Manufacturing a thermal substrate contact further includes operations of etching a first opening through the layer of semiconductor material to expose the oxide layer; etching a second opening through the first opening to expose the substrate; and filling the first opening and the second opening with a conductive material.

Method of making a semiconductor device having a thermal contact

A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.

Method of manufacturing a super junction structure and super junction structure

A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

Method of making semiconductor device having buried bias pad

An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. A thermal substrate contact increases the ability to remove heat produced from the integrated circuit transistors out of the integrated circuit. A thermal substrate contact which traverses the oxide layer over a substrate provides a secondary path for heat out of an integrated circuit (or, alternatively, out of a substrate through the integrated circuit) to cool the integrated circuit.

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Hsinchu, Taiwan

Feng Han