Applied Materials, Inc.

Novellus Systems Incorporated

Asml Netherlands B.v.

Feng Chen

Tae Hong Ha

Wenjing Xu

Raashina Humayun

Lu Chen

Xianmin Tang

Michal Danek

Anand Chandrashekar

Zhiyuan Wu

Mehul B Naik

Kartik Bhupendra Shah

He Ren

Roey Shaviv

Adolph Miller Allen

Kaihan Abidi Ashtiani

Karl B Levy

Xiangjin Xie

Kevin Kashefi

Satish Radhakrishnan

Mei Yin Chang

David P Thompson

Feng Quan Liu

Seshadri Ganguli

Jeffrey W Anthis

Yen-Wen Lu

Gang Shen

Lana Hiului Chan

Juwen Gao

Michael Sterling Jackson

Karthik Ramanathan

Tsung-Han Yang

Deqi Wang

Alexander Jansen

Yufei Hu

Karthikeyan Balaraman

Carmen Leal Cervantes

Cheng-Hsiung Matthew Tsai

Yongfa Fan

Xinyuan Chong

Weize Hu

Abhishek Manohar

Anil Mane

Mitrabhanu Sahu

Suketu Arun Parikh

Sang Ho Yu

Fuhong Zhang

Youping Zhang

Yi Xu

Jen-Shiang Wang

Rui Li

Lanlan Zhong

Aravind Kamath

Xi Chen

Chi-Hsiang Fan

Shi You

Yu Zhao

Yizhak Sabba

Jan Wouter Bijlsma

Leiwu Zheng

Mirko Glass

Christina L Engler

Yan Guan

Michael Danek

Matteo Alessandro Francavilla

Ge Qu

Yong Jin Kim

Jin Cheng

Wangshi Zhao

Dianwen Zhu

Ziyang Ma

Embodiments of the disclosure relate to methods and materials for forming barrier layers with enhanced barrier performance and/or reduced via resistance. Some embodiments of the disclosure provide methods for passivating a metal surface by exposing the metal surface to a metal complex comprising an organic ligand with at least three carbon atoms and a double or triple bond that eta bonds with a central metal atom. Some embodiments provide barrier layers within vias which enable a reduction in resistance of at least 25% as a result of thinner barrier layers with equivalent barrier properties.

Methods and materials for enhanced barrier performance and reduced via resistance

Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Method of forming a metal liner for interconnect structures

Methods for selective deposition are described herein. Further, methods for improving selectivity comprising an ammonia plasma pre-clean process are also described. In some embodiments, a silyl amine is used to selectively form a surfactant layer on a dielectric surface. A ruthenium film may then be selectively deposited on a conductive surface. In some embodiments, the ammonia plasma removes oxide contaminations from conductive surfaces without adversely affecting the dielectric surface.

Methods of selective deposition

Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

Low resistance and high reliability metallization module

Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

Reverse selective etch stop layer

Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

Methods and apparatus for precleaning and treating wafer surfaces

A patterning process modeling method includes determining, with a front end of a process model, a function associated with process physics and/or chemistry of an operation within a patterning process flow; and determining, with a back end of the process model, a predicted wafer geometry. The back end includes a volumetric representation of a target area on the wafer. The predicted wafer geometry is determined by applying the function from the front end to manipulate the volumetric representation of the wafer. The volumetric representation of the wafer may be generated using volumetric dynamic B-trees. The volumetric representation of the wafer may be manipulated using a level set method. The function associated with the process physics and/or chemistry of the operation within the patterning process flow may be a velocity/speed function. Incoming flux on a modeled surface of the wafer may be determined using ray tracing.

Method for patterning process modelling

Process recipe data associated a process to be performed for a substrate at a process chamber is provided as input to a trained machine learning model. A set of process recipe settings for the process that minimizes scratching on one or more surfaces of the substrate is determined based on one or more outputs of the machine learning model. The process is performed for the substrate at the process chamber in accordance with the determined set of process recipe settings.

Reducing substrate surface scratching using machine learning

Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

Ruthenium liner and cap for back-end-of-line

Ruthenium liner and cap for back-end-of-line applications

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

Binary metal liner layers

Methods and systems for reducing substrate particle scratching using machine learning are provided. A machine learning model is trained to predict process recipe settings for a substrate temperature control process to be performed for a current substrate at a manufacturing system. First training data and second training data are generated for the machine learning model. The first training data includes historical data associated with prior process recipe settings for a prior substrate temperature control process performed for a prior substrate at a prior process chamber. The second training data is associated with a historical scratch profile of one or more surfaces of the prior substrate after performance of the prior substrate temperature control process according to the prior process recipe settings. The first training data and the second training data are provided to train the machine learning model to predict which process recipe settings for the substrate temperature control process to be performed for the current substrate correspond to a target scratch profile for one or more surfaces of the current substrate.

A method for determining an etch profile is described. The method includes determining a masking layer profile. Loading information can be determined. The loading information indicates dependence of an etch rate for the masking layer profile on a quantity and pattern of material being etched. Flux information can be determined. The flux information indicates dependence of the etch rate on an intensity and a spread angle of radiation incident on the masking layer profile. Re-deposition information can be determined. The re-deposition information indicates dependence of the etch rate on an amount of material removed from the masking layer profile that is re-deposited back on the masking layer profile. An output etch profile for the layer of the wafer is determined based on the loading information, the flux information, and/or the re-deposition information.

Method for determining an etch profile of a layer of a wafer for a simulation system

Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

Methods and apparatus for intermixing layer for enhanced metal reflow

Processing methods comprising exposing a substrate to a first reactive gas comprising an ethylcyclopentadienyl ruthenium complex or a cyclohexadienyl ruthenium complex and a second reactive gas comprising water to form a ruthenium film are described.

Water assisted highly pure ruthenium thin film deposition

Growing community of inventors

Milpitas, CA, United States of America

Feng Chen