Sandisk Technologies Inc.

Airhop Communications, Inc.

Fei Zhou

Raghuveer S Makala

Rahul Sharangpani

Adarsh Rajashekhar

Senaka Kanakamedala

Yanli Zhang

Seung-Yeul Yang

Yao-Sheng Lee

Ramy Nashed Bassely Said

Keerti Shukla

Fumitaka Amano

Hanson On

Zhixin Cui

Naoki Takeguchi

Yusuke Mukae

Zaijin Guan

Kartik Sondhi

Masaaki Higashitani

Johann Alsmeier

Christopher John Petti

Tatsuya Hinoue

Masanori Tsutsumi

Akio Nishida

Bhagwati Prasad

Srikanth Ranganathan

Kensuke Yamaguchi

Somesh Peri

Genta Mizuno

Chun Ge

Tomoyuki Obu

Tiffany Santos

Yujin Terasawa

Joyeeta Nag

Toshihiro Iizuka

Tomohiro Uno

Yingda Dong

James K Kai

Ching-Huang Lu

Hiroyuki Kinoshita

Takashi Whitney Orimoto

Kiyohiko Sakakibara

Ashish Kumar Baraskar

Peng Zhang

Xue Bai Pitner

Yusuke Ikawa

Cheng-Chung Chu

Roshan Jayakhar Tirukkonda

Eisuke Takii

Stephen Ross

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Three-dimensional memory device containing variable thickness word lines with reduced length metal nitride diffusion barriers and methods for forming the same

A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

Three-dimensional memory device containing epitaxial pedestals and top source contact

A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof

A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Three-dimensional memory device with vertical word line barrier and methods for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.

Three-dimensional memory device with word-line etch stop liners and method of making thereof

Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Implementation of deep neural networks for testing and quality control in the production of memory devices

A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Semiconductor device containing bit lines separated by air gaps and methods for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

Three-dimensional memory device including discrete charge storage elements with laterally-protruding profiles and methods of making thereof

Three-dimensional memory device with electrically conductive layers containing vertical tubular liners and methods for forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.

Three-dimensional memory device including discrete charge storage elements and methods for forming the same

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San Jose, CA, United States of America

Fei Zhou