Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Smic New Technology Research and Development (shanghai) Corporation

Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing (beijing) International Corporation

Opple Lighting Co., Ltd.

Semiconductor Manufacturing International (shanghai) Corporation Shanghai, China

Semiconductor Manufacturing International (beijing) Corporation Beijing, China

Semiconductor Manufacturing Int. (shanghai) Corp.

Semiconductor Manufacturing Int. (beijing) Corp.

Semiconductor Manufacturing International Corp.

Fei Zhou

Zhongshan Hong

Jun Yang

Jianhua Ju

Bin Lin

Jianming Xia

Xiaohua Tu

Changfu Xue

A semiconductor device is provided in the present disclosure. The semiconductor device includes a substrate, a plurality of fins formed on the substrate, a dummy gate structure formed across the plurality of fins and on the substrate, a first sidewall spacer formed on a sidewall of the dummy gate structure, an interlayer dielectric layer formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer, and a second sidewall spacer formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer. The top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure.

Semiconductor device

A semiconductor structure includes a base substrate including a first region and a second region. The semiconductor further includes a first fin member located over the first region, a second fin member located over the second region, a first dummy gate across a surface of the first fin member, and a second dummy gate across a surface of the second fin member. A first opening is formed in the first fin member located on each side of the first dummy gate, a second opening is formed between two adjacent first channel layers, a third opening is formed in the second fin member located at each side of the second dummy gate, and a fourth opening is formed between two second channel layers. The semiconductor structure still further includes a first inner spacer located in the second opening, and a second inner spacer located in the fourth opening.

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for forming the same are provided. One form of a semiconductor structure includes: a substrate including a device unit region, where the device unit region includes a first sub-unit region configured to form a first device and a second sub-unit region configured to form a second device, where a driving current of the first device is greater than a driving current of the second device; a fin protruding from the substrate; a first gate spanning the fin in the first sub-unit region; and a second gate spanning the fin in the second sub-unit region. In some implementations, the second sub-unit region is disposed in the device unit region, and the second device generates less heat than the first device. Therefore, compared with a solution in which the device unit region includes only a first device region, overall heat from the device unit region can be reduced, thus ameliorating a self-heating effect in the device unit region and enhancing the performance of semiconductors.

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. One form of the method includes: providing a base, where a channel stack and a tear-off structure span the channel stack being formed on the base, and the channel stack including a sacrificial layer and a channel layer; forming a groove in channel stacks on both sides of a gate structure; laterally etching the sacrificial layer exposed from the groove to form a remaining sacrificial layer; forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer; forming an interlayer dielectric layer on the base; etching the interlayer dielectric layer on one side of the source region to expose a surface of the channel layer corresponding to the source region; etching the interlayer dielectric layer on one side of the drain region to expose the surface of the channel layer corresponding to the drain region; forming a first metal silicide layer on a surface of the channel layer corresponding to the source region; forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region; forming a first conductive plug covering the first metal silicide layer and a second conductive plug covering the second metal silicide layer. In the present disclosure, contact resistance of the first conductive plug, the second conductive plug, and the source/drain doped region is reduced.

Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.

Semiconductor structure with a contact to source/drain layers and fabrication method thereof

A semiconductor structure and a method for forming the same are provided. One form of a method for forming a semiconductor structure includes: providing a base, the base including a first device region and a second device region, the base including an initial substrate and one or more initial channel stacks located on the initial substrate, and the initial channel stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a discrete combined pattern on the initial channel stack, the combined pattern including a mandrel layer and a spacer layer located on a side wall of the mandrel layer, and the combined pattern exposing a boundary between the first device region and the second device region; forming a dielectric wall running through the initial channel stack at the boundary between the first device region and the second device region; and removing the mandrel layer. In embodiments and implementations of the present disclosure, the spacer layer has good uniformity, and the initial channel stack is etched by using the spacer layer as a mask to form a separate channel stack which has good morphology uniformity, which is conducive to improving the uniformity of the semiconductor structure performance.

A mode setting method and a mode setting device for a monitoring system are provided. The mode setting method includes: selecting one or a plurality of monitoring objects; selecting a corresponding display template from preset display templates for each of the one or the plurality of monitoring objects, and associating and packaging each of the one or the plurality of monitoring objects and the selected display template in a one-to-one correspondence, and generating one or a plurality of single display units; selecting a single display unit from the generated single display units according to a monitoring scene; and placing the selected single display unit into a corresponding block of a monitoring interface layout of the monitoring system, and storing the same.

Mode setting method and device of monitoring system

Semiconductor devices is provided. The semiconductor structure includes a semiconductor substrate having a middle region and an edge region adjacent to the middle region, a plurality of first fins formed on the middle region of the semiconductor substrate, a plurality of second fins formed on the edge region of the semiconductor substrate, a first adjustment layer formed on sidewall surfaces of the plurality of first fins and on the middle region of the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and with a top surface lower top surfaces of the plurality of first fins and the plurality of second fins.

A semiconductor device is provided. The semiconductor device includes: a substrate and first gate structures and source/drain doped layers on the substrate. Each of the source/drain doped layers is located at two sides of one first gate structure. The semiconductor device further includes a dielectric layer on the substrate. The dielectric layer contains first grooves, exposing the source/drain doped layers, wherein each first groove includes a first-groove bottom part and a first-groove top part located above the first-groove bottom part, and a size of the first-groove top part is larger than a size of the first-groove bottom part. The semiconductor device further includes a first conductive structure located in the first-groove bottom part, an insulating layer located in the first-groove top part and on the first conductive structure, and a second conductive structure located in the dielectric layer and connected to the first gate structure.

Semiconductor device and forming method thereof

A semiconductor structure includes a substrate; and a fin structure disposed on the substrate. The fin structure includes a channel region, a source region, and a drain region. The channel region is located between the source region and the drain region. The channel region includes a first nanowire and a second nanowire above the first nanowire. The first nanowire contains first threshold-voltage adjustment ions, and the second nanowire contains second threshold-voltage adjustment ions. A first opening is formed between the first nanowire and the substrate, and between the source region and the drain region, and a second opening is formed between the first nanowire and the second nanowire, and between the source region and the drain region. The first threshold-voltage adjustment ions are different from the second threshold-voltage adjustment ions in type, concentration, or a combination thereof.

Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate, a first conductive layer on the first conductive layer and the second doped layer, a second conductive layer on a surface of the first conductive layer, and a third conductive layer on a contact region of the first gate structure. The second region is between the first region and the third region. The contact region is at a top of the first gate structure. A minimum distance between the second conductive layer and the third conductive layer is greater than zero.

A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region.

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; fins on the semiconductor substrate; an isolation layer formed on the semiconductor substrate and between adjacent fins; and gate structures on sides of the isolation layer. The isolation layer has a top surface higher than top surfaces of the fins and passes through the fins along a direction perpendicular to an extending direction of the fins and in parallel with a surface of the semiconductor substrate.

Semiconductor device with fins

Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate, a plurality of fins protruding from the semiconductor substrate, an isolation layer formed on the fins and with a bandgap greater than a bandgap of the fins, and a first channel layer formed on the isolation layer and isolated from the isolation layer.

Semiconductor structure

A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.

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Shanghai, China

Fei Zhou