Micron Technology Incorporated

Aptina Imaging Corporation

Intel Corporatino

Fei Wang

Kunal Shrotri

John David Hopkins

Anton P Eppich

Xinya Lei

William Arthur Stanton

Anish A Khandekar

Matthew Park

Kunal R Parekh

Martin Ceredig Roberts

Justin B Dorhout

Chet E Carter

Aaron R Wilson

Tom Jibu John

Vinayak Shamanna

Ian C Laboriante

Ryan L Meyer

Derek F Lundberg

Pary Baluswamy

Chung-Yi Lee

Matthew J King

Jie Li

Jeffery B Hull

Jun Fang

Rutuparna Narulkar

Ezequiel Vidal Russell

Zhixin Xu

Saniya Rathod

Duo Mao

Ee Ee Eng

Dong Liang

Jun Liu

Gordon A Haller

Hongbin Zhu

Wei Yeeng Ng

Jun Zhao

Wesley O McKinsey

Zhong Shi

Jeremy F Adams

Mark A Levan

Zhiqiang Xie

A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

Semiconductor devices comprising carbon-doped silicon nitride and related methods

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

A method of forming SiN, where 'x' is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising SiN, where 'x' is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

Programmable charge storage transistor, an array of elevationally-extending strings of memory cells, methods of forming Si3Nx, methods of forming insulator material that is between a control gate and charge-storage material of a programmable charge-storage transistor, methods of forming an array of elevationally-extending strings of memory cells, a programmable charge-storage transistor manufactured in accordance with methods, and an array of elevationally-extending strings of memory cells man

Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

Solid state memory device, and manufacturing method thereof

A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and HPOthan does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and HPOto increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials

Methods of forming sin, methods of forming insulator material between a control gate and charge-storage material of a programmable charge-storage transistor, and methods of forming an array of elevationally-extending strings of memory cells and a programmable charge-storage transistor manufactured in accordance with methods

Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.

Sub-resolution assist devices and methods

A photomask includes a substrate having a device region and an adjacent edge region over transparent material. The device region includes spaced primary features of constant pitch at least adjacent the edge region. The edge region includes spaced sub-resolution assist features of the constant pitch of the spaced primary features at least adjacent the device region and which are off-phase by from about 30&#xb0; to about 150&#xb0; from +/&#x2212;180&#xb0;. Additional embodiments, including methods, are disclosed.

Photomasks, methods of forming a photomask, and methods of photolithographically patterning a substrate

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Boise, ID, United States of America

Fei Wang