Micron Technology Incorporated

Stmicroelectronics Gmbh

Faxing Che

Hong Wan Ng

Yeow Chon Ong

Wei Yu

Yonggang Jin

Ling Pan

Xavier Baraton

Shin Yueh Yang

Lin Bu

A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

Methods and apparatus for using spacer-on-spacer design for solder joint reliability improvement in semiconductor devices

A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.

Semiconductor devices with flexible spacer including a support structure and methods of making the same

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Reducing warpage for fan-out wafer level packaging

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Singapore, Singapore

Faxing Che