Applied Materials, Inc.

Philips Semiconductors Inc.

Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Philips Semiconductor, Inc.

Nxp B.v.

Faran Nouri

Lori D Washington

Sunderraj Thirupapuliyur

Victor Moroz

Yonah Cho

Christopher Sean Olsen

Thai Cheng Chua

Vijay Parihar

Samit S Sengupta

Tammy D Zheng

Martin Manley

Eun-Ha Kim

Tammy Zheng

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

NMOS transistor devices and methods for fabricating same

Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Methods for forming a transistor and modulating channel stress

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Methods for forming a transistor

Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity.

Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

Methods for contact resistance reduction of advanced CMOS devices

A SiONgate dielectric and a method for forming a SiONgate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NHand then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiONgate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NHin one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.

Method of forming a silicon oxynitride layer

In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (V,versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in V,versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, V,roll off due to boron segregation is also minimized.

Method for suppressing narrow width effects in CMOS technology

An ion implanting process allows for shallow source and drain junctions of the transistor. According to one example embodiment, a BARC layer is formed over a gate, and a poly-crystalline or amorphous silicon shield is deposited over the source and drain regions, then the BARC and silicon are chemically mechanically polished. The poly-crystalline or amorphous silicon shield absorbs the initial impact the dopant species of ion implantation and reduces the incidence of irreversible source/drain crystal damage caused by the process. After the ion implantation, the species implanted in the poly or amorphous silicon is diffused into the source/drain regions by annealing. An additional siliciding of the poly or amorphous silicon covering the source and drain minimizes the need for deeper source/drain junctions and hence improves short-channel properties.

Method of manufacturing shallow source/drain junctions in a salicide process

A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and V,roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed. The STI region is filled with an oxide layer and is planarized until the oxide layer is substantially flush with the nitride layer. The resulting oxide layer is wider and protects the STI region from subsequent processing.

Method for forming isolation areas with improved isolation oxide

The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

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Los Altos, CA, United States of America

Faran Nouri