Intel Corporation

Fangwen Fu

James M Holland

Satya N Yedidi

Jill MacDonald Boyce

Abhishek R Appu

Keith W Rowe

Sumit Mohan

Joydeep Ray

Sang-Hee Lee

Subramaniam M Maiyuran

Varghese George

Mike MacPherson

Atthar H Mohammed

Hiu-Fai R Chan

Supratim Pal

Altug Koker

Stanley J Baran

Jorge E Parra

Chandra S Gurram

Jong Dae Oh

Srinivasan Embar Raghukrishnan

Sasikanth Avancha

Jiasheng Chen

Sabareesh Ganapathy

Vasanth Ranganathan

Ya-Ti Peng

Dhiraj D Kalamkar

Wen-Fu Kao

Hong Jiang

Guei-Yuan Lueh

Lidong Xu

Ben J Ashbaugh

Naveen K Mellempudi

Ashutosh Garg

Qian Xu

Jason Daniel Tanner

James A Valerio

Dipankar Das

Wei-Yu Chen

Sang-hee Lee

Zhijun Lei

Chunhui Mei

Vidhya Krishnan

Iole Moccagatta

Dmitry E Ryzhov

Wei Xiong

Changwon D Rhee

Haihua Wu

Shuai Mu

Dharma Teja Vooturi

Prathamesh Raghunath Shinde

Tuyet-Trang Lam Piel

Yue Qi

A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.

Systolic array having support for output sparsity

A processing apparatus includes a general-purpose parallel processing engine including a set of multiple processing elements including a single precision floating-point unit, a double precision floating point unit, and an integer unit; a matrix accelerator including one or more systolic arrays; a first register file coupled with a first read control circuit, wherein the first read control circuit couples with the set of multiple processing elements and the matrix accelerator to arbitrate read requests to the first register file from the set of multiple processing elements and the matrix accelerator; and a second register file coupled with a second read control circuit, wherein the second read control circuit couples with the matrix accelerator to arbitrate read requests to the second register file from the matrix accelerator and limit access to the second register file by the set of multiple processing elements.

Register file for systolic array

An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

Supporting 8-bit floating point format operands in a computing architecture

Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

Architecture for block sparse operations on a systolic array

A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.

Dual pipeline parallel systolic array

An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

Matrix operation optimization mechanism

Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Hierarchical thread scheduling based on multiple barriers

Dot product operations on sparse matrix elements

A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.

Lossless pixel compression based on inferred control information

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

Power-based and target-based graphics quality adjustment

An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.

MV/mode prediction, ROI-based transmit, metadata capture, and format detection for 360 video

The present techniques include deriving a threshold to maintain an encoding bitrate and determining a percentage of change of a current frame N based on an impact to a bitrate budget. The present techniques also include marking a reference frame N&#x2212;1 as non-referenceable in response to the percentage of change being smaller than the threshold and encoding a static portion of frame N as a skip and encoding a non-static portion of frame N by referencing the reference frame N&#x2212;1. Finally, the present techniques include overwriting a surface of the reference frame N with portions of the reference frame N&#x2212;1 that have changed as compared to frame N.

Selective coding

A system includes a camera to capture real world content and a semiconductor package apparatus. The semiconductor package apparatus includes a substrate and logic. The logic includes a graphics pipeline to generate rendered content, a base layer encoder to encode real world content into a base layer and a first layer encoder to encode rendered content into a first non-base layer, a multiplexer to interleave the base layer with the first non-base layer to obtain a single output signal having mixed reality content, and a transmitter to transmit the single output signal. The system further includes a second layer encoder to encode map data into a second non-base layer. The multiplexer to interleave the second non-base layer with the first non-base layer and the base layer. The first and second layer encoders encode the rendered content and the map data into overlay auxiliary pictures.

Mixed reality coding with overlays

Growing community of inventors

Folsom, CA, United States of America

Fangwen Fu