Promos Technologies, Inc

Fang-Yu Yeh

Chi Chou Lin

Chun-Che Chen

Chuang-Hsiang Chen

Han-Chih Lin

Chia-Yao Chen

Chin-Sheng Chen

A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Two-step GC etch for GC profile and process window improvement

A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Method of forming semiconductor device with non-conformal liner layer that is thinner on sidewall surfaces

A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process is performed. A gate dielectric layer, a first conductive layer and a second conductive layer are sequentially formed inside the first opening. The second conductive layer completely fills the first opening. A portion of the first conductive layer and the second conductive layer are removed so that the upper surface of the first conductive layer and the second conductive layer is slightly below the upper surface of the substrate and hence forms a second opening. A cap layer is formed in second opening and then the mask layer is removed. A source/drain region is formed in the substrate on each side of the first conductive layer. An inter-layer dielectric layer is formed over the substrate. Finally, using the cap layer as a self-aligned mask, a contact opening is formed in the inter-layer dielectric layer.

Semiconductor device and manufacturing method thereof

A method for forming contacts in a semiconductor device including a plurality of active devices formed over a substrate that includes depositing a first layer of dielectric material over the substrate and plurality of active devices, forming a first opening in the first layer of dielectric material, depositing a second layer of dielectric material over the first layer of dielectric material and in the first opening, providing a mask over the second layer of dielectric material, wherein the mask material is distinguishable over silicon oxides, and forming a second opening and a third opening in the second layer of dielectric material, wherein the second opening is aligned with the first opening and exposes a first silicide of a first active device, and the third opening exposes one of diffused regions of a second active device.

Growing community of inventors

Hsinchu, Taiwan

Fang-Yu Yeh