Taiwan Semiconductor Manufacturing Comp. Ltd.

Fang Wen Tsai

Wen-Chih Chiou

Shin-Puu Jeng

Chen-Hua Douglas Yu

Jing-Cheng Lin

Chen-Yu Tsai

Hsin Chang

Hsin-Yu Chen

Po-Hao Tsai

Cheng-Lin Huang

Weng-Jin Wu

Chi-Chun Chen

Matt Yeh

Shun Wu Lin

Chia-Ho Chen

Yan-Fu Lin

Shih-Hui Wang

Chien-Ming Chiu

Ya-Hsi Hwung

Tien-I Bao

Kuang-Yuan Hsu

Shwang-Ming Jeng

Zhen-Cheng Wu

Bor-Wen Chan

Kuang-Wei Cheng

Chih-Lung Lin

Chyi-Shyuan Chern

Zin-Chang Wei

Jiung Wu

Li-Shiun Chen

I-i Chen

Jim Cy Huang

Ming-Jun Wang

Jiann Sheng Chang

Yi Chou Lai

A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Alignment marks in substrate having through-substrate via (TSV)

A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.

Through silicon via structure

A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Method for through silicon via structure

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Alignment mark and method of formation

An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports.

Reconfigurable guide pin design for centering wafers having different sizes

A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Copper bump structures having sidewall protection layers

The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region.

Double treatment on hard mask for gate N/P patterning

Method for producing a protective structure

Growing community of inventors

Hsin-Chu, Taiwan

Fang Wen Tsai