Huazhong University of Science and Technology

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Yangtze Memory Technologies Co., Ltd.

State Grid Hubei Electric Power Research Institute

Fan Yang

Xiangshui Miao

Sheng Hu

Xingsheng Wang

Chengxu Wang

Wei Jiang

Wei Hu

Jiakuan Yang

Sha Liang

Huijie Hou

Jingping Hu

Wanting Deng

Wenbo Yu

Zeyang Tang

Zhichun Yang

Yu Shen

Liang Huang

Lingjun Zhou

Xiao Guo

Shushan Yuan

Ning Zhang

Huabo Duan

Shuai Chen

Menghua Huang

Yinghao Ma

Fangbin Yan

Lei Su

Yao Yao

Yang Lei

Examples of the present disclosure provide a memory device and an operation method thereof, and a memory system. The memory device includes: a memory cell array including memory cells, wherein the memory cells are divided into memory planes; bit lines; page buffer circuits, wherein each of the page buffer circuits includes page buffer groups, and corresponds to one of the memory planes, and the page buffer circuit performs a buffer operation in response to a buffer operation command; and a control logic coupled to the page buffer groups and configured to: for each of the memory planes, provide the buffer operation command to the plurality of page buffer groups, and control performing time periods for the page buffer groups to perform the buffer operation such that some performing time periods among the plurality of performing time periods overlaps.

Memory devices and operation methods thereof, and memory systems for managing page buffer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The method of manufacturing the semiconductor device includes: forming a trench fill structure in a pixel region of a substrate, where a high-k dielectric layer is sandwiched between a side wall of a fill material in the trench fill structure and the substrate; forming a plug structure in a pad region of the substrate; covering a surface of the substrate in the pixel region and the pad region with a buffer dielectric layer; etching the buffer dielectric layer to form first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer in the pixel region.

Semiconductor device and manufacturing method therefor

A flow electrode capacitive deionization system and a method for recovering phosphorus in phosphogypsum leachate and synchronous performing brine desalination belong to the technical field of wastewater treatment and recycling. The flow electrode capacitive deionization system includes a phosphorus recovery electrodeionization module and a desalination electrodeionization module. A first flow electrode solution reservoir, a phosphorus recovery electrodeionization module cathode flow electrode chamber, and a desalination electrodeionization module anode flow electrode chamber are interconnected in a circulation. A second flow electrode solution reservoir, a phosphorus recovery electrodeionization module anode flow electrode chamber, and a desalination electrodeionization module cathode flow electrode chamber are interconnected in a circulation. Two independent flow electrode solution circulation loops are formed. The phosphogypsum leachate enters the phosphorus recovery electrodeionization module and phosphorus is enriched into a flow electrode solution. A phosphorus-rich solution is reacted with a ferrous solution under an oxygen-free condition to generate vivianite [Fe(PO)·8HO].

Flow electrode capacitive deionization system and method for recovering phosphorus in phosphogypsum leachate and synchronous performing brine desalination

A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.

High-speed and large-current adjustable pulse circuit, operating circuit and operating method of phase-change memory

A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.

Read and write circuit of three-dimensional phase-change memory

A semiconductor device and a method of fabricating thereof are disclosed. The method of fabricating a semiconductor device includes: forming a trench fill structure in a substrate in a pixel area; covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure; etching the buffer dielectric layer to form a first opening, which exposes at least a portion of the substrate surrounding sidewalls of a top of the trench fill structure and/or at least a portion of the top of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer, wherein the metal grid layer fills the first opening and is electrically connected to the exposed portion of the substrate and/or the exposed portion of the trench fill structure. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate and/or part of the top of the trench fill structure, thus allowing optimization or amelioration of the semiconductor device's electrical performance.

Semiconductor device and method of fabricating the same

A device for simulating intermittent arc grounding faults in a power distribution network includes a sliding rail, a first and a second support frames, an insulated electrode disk, and an electrode disk motor. The first support frame is fixed on the left side of the slide rail, and the position of the second support frame relative to the first support frame can be adjusted through the sliding rail. The second support frame is provided with an electrode disk motor for driving the insulated electrode disk to rotate. An upper and a lower conductive bars are installed on the first support frame, their adjacent ends provided with an upper and a lower arc-shaped conductor sheets, and the insulated electrode disk having two circles of conductive pillars is located between the conductor sheets. The conductor sheets are respectively installed on the side of the conductive bars close to the conductive pillar.

Device and method for simulating intermittent arc grounding faults of power distribution network

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Hubei, China

Fan Yang