Taiwan Semiconductor Manufacturing Comp. Ltd.

Fa-Yuan Chang

Hua-Shu Ivan Wu

Chia-Shiung Tsai

Chih-Wei Chang

Yuan-Chih Hsieh

Ming-Chyi Liu

Clinton Chao

Gwo-Yuh Shiau

Kai-Chih Liang

Tsung-Mu Lai

Hsu Ming Cheng

I-Ching Lin

Tsung-Cheng Huang

Shih-Fang Chen

Ming-Yeon Hung

Ching-Chung Pai

Nick Y M Shen

Cheng-Cheng Chang

Yuan-Hao Chien

Chin-Hsiang Ho

Chu-Wei Cheng

Cheng-Ting Tseng

Chin-Chang Chen

Hsi-Lung Lee

A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

Semiconductor fabrication method suitable for MEMS

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Process for wafer bonding

A system and a method of testing a semiconductor die is provided. An embodiment comprises a plurality of tips that each comprise a substrate with a conductive via, a first dielectric layer with vias connected to the conductive via, a second dielectric layer with vias over the first dielectric layer, and a metal layer over the second dielectric layer. Additional dielectric layers with vias may be used. This tip is electrically connected to a redistribution line that routes signals between the tip to electrical connections on a space transformation layer. The space transformation layer is electrically connected to a printed circuit board using, for example, a spring loaded connection such as a pogo pin. The space transformation layer is aligned onto the printed circuit board by a series of guidance mechanisms such as guide pins or smooth fixtures, and the planarity of the tips is adjusted by adjusting the screws.

Ultra-fine pitch probe card structure

A wafer transfer system having a temperature control apparatus. The temperature control apparatus is constructed and arranged so that a material, element, or atomic particle may flow therethrough to heat or cool a wafer carried by the wafer transfer system. The material, element or atomic particle flowing through the temperature control apparatus causes heat to be pumped to or from an upper surface or lower surface. Preferably the temperature control apparatus is a thermoelectric device. Preferably the thermoelectric device includes a plurality of alternating N-type and P-type semiconductor pellets arranged electrically in series and thermally in parallel, and connected to a DC power supply. A switch or relay is provided for altering the direction of current flow to the thermoelectric device from a DC supply.

Wafer transfer system with temperature control apparatus

A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing hard mask layer, where the blanket silicon containing hard mask layer is formed from a silicon containing material chosen from the group of silicon containing materials consisting of silicon oxide materials, silicon nitride materials, silicon oxynitride materials and composites of silicon oxide materials, silicon nitride materials and silicon oxynitride materials. There is then formed upon the blanket silicon containing hard mask layer a patterned photoresist layer. There is then etched through a first plasma etch method the blanket silicon containing hard mask layer to form a patterned silicon containing hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorine and carbon containing etchant source gas and a first bromine containing etchant source gas. Finally, there is then etched in-situ through a second plasma etch method the blanket silicon layer to form an at least partially etched silicon layer while employing the patterned photoresist layer and the patterned silicon containing hard mask layer as a second etch mask. The second plasma etch method employs a second etchant gas composition comprising a second fluorine and carbon containing etchant source gas, a second bromine containing etchant source gas and a chlorine containing etchant source gas.

In-situ sequential silicon containing hard mask layer/silicon layer

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Taipei, Taiwan

Fa-Yuan Chang