Integrated Silicon Solution Incorporated

Azalea Microelectronics Corporation

Eung Joon Park

Hsi-Hsien Hung

Ali Pourkeramati

Hsiao-Lun Lee

In accordance with the present invention, a low VCC operational non-volatile memory cell includes a drain region and a source region separated by a channel region. A tunneling dielectric layer extends over the channel region and a portion of the drain and source regions. A floating gate extends over the tunneling dielectric. An insulating layer extends over the floating gate, and a control gate extends over the insulating layer. The channel region is implanted with a relatively low dosage of channel threshold enhancement impurities or halo impurities to obtain a low initial Vt in the range of, for example, OV to 0.8V. The low initial Vt enables a low program Vt target ,e.g., 4V or less, which in turn enables the use of double-diffused N&plus;, N&minus; drain or source junctions with the N&plus; region being inside the N&minus; region. The memory cell is programmed through hot electron injection from a channel region near the N&minus; region to the floating gate, and is erased through Fowler-Nordheim tunneling of electrons from the floating gate to an area of the N&plus; region near the N&minus; region. Thus, the N&minus; region separates the erase area in the N&plus; region from the program area in the channel region.

Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions

A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2 and high at t5). The t1 .phi.1 positive transient is AC-coupled to M1's drain, and a smaller fraction of the transient is coupled to M1's gate, precharging M1, which begins to turn-on. The .phi.3 t2 negative transient is AC-coupled to M1's source, increasing M1 gate-source potential, which more fully turns-on M1. The .phi.2 t3 positive transient is coupled to M1's gate, turning-on M1 very hard. A phase clock generator outputting square-wave, same-frequency signals having respective 90.degree. phase shifts that are frequency independent can be used to drive pump circuits and sequentially operated groups of pump circuits.

Charge pump system with improved programming current distribution

The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The redundant column decoder has a pull-up path and a parallel combination of n pairs of complementary pull-down paths. The pull-up path is connected to the pull-down paths at an output node, and the output signal is taken at this output node. Each pair of complementary pull-down paths has a first pull-down path and a second pull-down path. The first pull down path has a first non-volatile memory cell in series with and connected to a first address transistor. The first address transistor is also connected to the output node. The second pull-down path has a second non-volatile memory cell in series with and connected to a second address transistor. The second address transistor is also connected to the output node. At least one of the pull-down paths is conductive when the stored defective address does not match the presented address. Conversely, all of the pull-down paths are non-conductive when the stored defective address matches the presented address.

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Fremont, CA, United States of America

Eung Joon Park