Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Eun Sook Sohn

Jong Sik Paek

Won Chul Do

Tae Kyung Hwang

Won Joon Kang

Gi Jeong Kim

In Bae Park

Glenn A Rinne

Min Woo Lee

Chan Ha Hwang

Jin Young Kim

Do Hyung Kim

Byong Jin Kim

Seon Goo Lee

Choon Heung Lee

Bong Chan Kim

Sung Su Park

Sang Jae Jang

Sung Soon Park

Ho Choi

Ji Yeon Yu

A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.

Electronic package structure with reduced vertical stress regions

Electronic package structure with improved board level reliability

A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

Semiconductor device and manufacturing method thereof

An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.

Chip-scale electronic package structure with conductive connective element having increased surface area and laterally spaced connection points for improved connectivity

A semiconductor device and a fabrication method thereof are provided. An electrically conductive elastic member is formed on a semiconductor die, and a conductive bump is formed on the elastic member. Accordingly, since the conductive bump is formed on the elastic member, or to protrude from a top surface of the elastic member, the height and thus diameter of the conductive bump is reduced allowing a fine pitch to be realized. Further, the elastic member is elastic and thus mitigates external impacts from being transferred from the conductive bump to the semiconductor die.

Semiconductor device and fabricating method thereof

A semiconductor device is disclosed. A conductive pillar for electrically connecting a semiconductor die to a circuit board may be gradually slimmed from the semiconductor die to the circuit board. A dummy conductive layer may be disposed between the semiconductor die and the conductive pillar. A width of an opening for opening a pattern of the circuit board may range from about 50% to 90% of the width of the lower end of the conductive pillar. Accordingly, a mechanical stress is prevented from being transmitted from the conductive pillar to the semiconductor die, or is absorbed by the dummy conductive layer, and thus, preventing cracks of the semiconductor die and a dielectric layer having a low dielectric constant.

Semiconductor device capable of preventing dielectric layer from cracking

In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. The semiconductor device comprises a substrate having a conductive pattern formed thereon. In each embodiment of the semiconductor device, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. In certain embodiments, a semiconductor die which is electrically connected to the conductive pattern of the substrate may be fully or partially covered with a film-over-wire. Additionally, in each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

Package in package semiconductor device with film over wire

A semiconductor package assembly has a first semiconductor package. A plurality of first solder balls is attached to the first semiconductor package. A circuit board is provided having a plurality of mounting pads that is electrically connected to the plurality of first solder balls. A first underfill is disposed on each of the plurality of first solder balls. The first underfill is disposed on interfaces between each of the plurality of first solder balls and the first semiconductor package and each of the plurality of first solder balls and the circuit board. The first underfill is removed from an area between adjacent first solder balls.

Semiconductor device having improved contact interface reliability and method therefor

In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove. In this instance, conductive material layers may be disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires, with solder pads further bring electrically connected to respective ones of the conductive material layers and at least partially residing within the groove.

Reduced profile stackable semiconductor package

An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.

Growing community of inventors

Seoul, South Korea

Eun Sook Sohn