Hynix Semiconductor Inc.

Skhynix Inc.

Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Eun-Seok Choi

Hyun-Seung Yoo

Seung-Jin Yeom

Jung-Seok Oh

Young-Wook Lee

Won-Joon Choi

Ki-Hong Lee

Se-Jun Kim

Seiichi Aritome

Sang-on Choi

Won-chul Bang

Wook Chang

Dong-Yoon Kim

Moon-Shik Kang

Sung-jung Cho

Ki-Tae Lee

Ho-june Yoo

Mi-ra Yu

Se-Yun Lim

Kyoung-ho Kang

Gun-Woo Moon

Byung-Seok Soh

Sung-Wook Jung

In-Hey Lee

Sa-Yong Shim

Sang-Bum Lee

Soon-Yong Kweon

Jheen-Hyeok Park

Sang-Hyun Oh

Won-Chul Bang

Nam-Kyeong Kim

Jin-Yong Seong

Han-Soo Joo

Jong-koo Oh

Jin-hyuk Hong

Sung-Kye Park

Gyu-Seog Cho

Seok-Kiu Lee

Myung-Joong Youn

Hyun-Ki Yoon

Joon-kee Cho

Se-Ra Park

Chang-Soo Noh

You-Sun Ji

Gyo-Ji Kim

Sung-Joo Hong

Sang-On Choi

Yong-Wan Choi

Jong-Bo Moon

Hyun-A Song

Young-Kwang Seo

Sung-Jung Cho

Kyoung-Ho Kang

A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.

Nonvolatile memory device and method for fabricating the same

A semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2Nth rows, wherein N is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to Nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to Nth rows; a plurality of first pipe channels suitable for connecting the first to Nth rows of source-side half channels to the first to Nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (N+1)th to 2Nth rows of source-side half channels to the first to Nth rows of second drain-side half channels, respectively.

Semiconductor device

A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.

3D non-volatile memory device and method for operating and fabricating the same

A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

Method of fabricating a nonvolatile memory device with a vertical semiconductor pattern between vertical source lines

A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Non-volatile memory device and method for fabricating the same

Nonvolatile memory device with vertical semiconductor pattern between vertical source lines

A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.

Non-volatile memory device having three dimensional, vertical channel, alternately stacked gate electrode structure

A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Reading method of non-volatile memory device

A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

3D nonvolatile memory device including a plurality of channel contacts coupled to a plurality of channel layers and a plurality of section lines coupled to the plurality of channel contacts and method for fabricating the same

A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.

Growing community of inventors

Gyeonggi-do, South Korea

Eun-Seok Choi