Skhynix Inc.

Hynix Semiconductor Inc.

Eun-Jeong Kim

Jin-Yul Lee

Dong-Soo Kim

Han-Sang Song

Su-Ho Kim

Sung-Won Lim

Keun Hang Heo

Tae-Kyung Oh

Jee-Hyun Kim

Hyun-Jin Chang

Se-Aug Jang

Sang-Tae Ahn

Eun-Ha Lee

A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.

Semiconductor device having buried gate structure, method for manufacturing the same, and memory cell having the same

A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.

Isolation structure and method for manufacturing the same

Method of manufacturing isolation structure for semiconductor device

Method for manufacturing isolation structure

A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps.

Semiconductor device with air gaps and method for fabricating the same

A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material.

Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same

A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process.

Method for forming isolation layer of semiconductor device

A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars.

Growing community of inventors

Gyeonggi-do, South Korea

Eun-Jeong Kim