Tohoku University

Globalwafers Japan Co., Ltd.

Power Spin Inc.

Etsuo Fukuda

Koji Izunome

Takashi Ishikawa

Tetsuo Endoh

Shoji Ikeda

Haruo Sudo

Tatsuhiko Aoki

Hisashi Matsumura

Satoru Araki

Toshimasa Namekawa

Hiroshi Yoshida

Kazutaka Kamijo

Moriya Miyashita

Takao Sakamoto

A silicon wafer is a Czochralski wafer formed of silicon. The wafer includes a bulk layer having an oxygen concentration of 0.5×10/cmor more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×10/cmor more.

Silicon wafer and method for producing silicon wafer

A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Semiconductor memory device and control device for semiconductor memory device

A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10atoms/cmor more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate

Growing community of inventors

Miyagi, Japan

Etsuo Fukuda