Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Eswar Vadlamani

Gopalakrishnan Perur Krishnan

Tarjinder Singh

Ramesha Doddamane

Tarjinder Singh Munday

A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator () that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (). An address range selector circuit () can limit the range of addresses generated by an address generator (). Once defective addresses for a first range have been detected, an address range selector circuit () can test another range. An entire address range can thus be tested regardless of the depth of a fault address store ().

Programmable address space built-in self test (BIST) device and method for fault detection

A parallel data transmission test system can include a receiver section () having input selector circuits (-O to-N) that provide a received test data to logic adjust circuits (-O to-N) that 'logically align' multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit () can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit ().

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Hyderabad Telangana, India

Eswar Vadlamani