International Business Machines Corporation

Erwin B Cohen

David Brian Stone

Wolfgang Sauter

Mark C H Lamorey

Anson Jay Call

Eric W Tremble

Dany Minier

Cedric Lichtenau

Stephen Victor Kosonocky

David L Questad

Peter Anthony Sandon

Paul David Kartschoke

Thomas Pflueger

Douglas Oliver Powell

Keith Robert Williams

Thomas Edward Cook

Paul Robert Walling

Jennifer V Muncy

Jay Gerald Heaslip

Mathew I Ringler

Miles G Canada

Marek Andrzej Orlowski

Ian R Govett

Martin P Goetz

J Richard Behun

A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

Split ball grid array pad for multi-chip modules

A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

Aspects of the present invention relate to land grid array socket cartridge structures. In one embodiment, a land grid array (LGA) cartridge structure includes: a deformable thin film having at least one aperture configured to hold a substantially liquid metal, whereby in a compressed state of the deformable thin film, the substantially liquid metal of the deformable thin film is configured to electro-mechanically couple a carrier and a socket base. Another embodiment includes a method of forming a LGA cartridge structure. The method includes: providing a deformable thin film having a first surface and a second surface, and forming at least one aperture within the deformable thin film through the first surface and the second surface, wherein the aperture is configured to hold a substantially liquid metal.

Land grid array (LGA) socket cartridge and method of forming

An electronic package has a cover or lid mounted onto a substrate to enclose an electronic device, and a liquid thermal interface material is subsequently inserted (through dispensing, injection molding or printing through apertures in the cover or lid) between the surface of the electronic device and the cover, and cured to a solid state.

Method of making an electronic package

A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

Elastic modulus mapping of a chip carrier in a flip chip package

A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.

Electromagnetic interference shield for semiconductors using a continuous or near-continuous peripheral conducting seal and a conducting lid

A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing power and performance, using a variety of combinable hardware and software techniques. Also, in a preferred embodiment, steps are used for maintaining coherency during cache resizing, including the handling of modified ('dirty') data in the cache, and steps are provided for partitioning a cache in one of several way to provide an appropriate configuration and granularity when resizing.

Method of dynamically controlling cache size

A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.

Clock dithering system and method during frequency scaling

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South Burlington, VT, United States of America

Erwin B Cohen