Lsi Logic Corporation

Altera Corporation

Lattice Semiconductor Corporation

Ernest Allen, Iii

David A Castaneda

Matthew C Hendricks

Eric F Chun

Miaw Looi

Alan Achor

According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.

Method for testing IDD at multiple voltages

According to one embodiment, a method of testing an integrated circuit is provided. A reference voltage is coupled to each of a first and second comparator integrated on the chip. A supply voltage is compared to the reference voltage in a comparator to determine overvoltage or undervoltage conditions. The results of the comparison are stored and sizing and placing of at least one decoupling circuit in the circuit design is made based on the stored determinations.

VDD over and undervoltage measurement techniques using monitor cells

A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.

Method for performing statistical post processing in semiconductor manufacturing using ID cells

A structure for programming a memory cell on an integrated circuit provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In an embodiment, the structure includes a conductive signal path extending through multiple horizontally conductive layers of the integrated circuit from a programming voltage pad (or node) to an input of the memory cell. The conductive signal path includes portions selected from multiple alternate path portions formed within the multiple horizontally conductive layers through which the signal path extends. An embodiment of a method for making a mask includes selecting one of multiple configurations of the programming structure portion to be formed using the mask. A computer-usable carrier medium may include digital representations of the alternative configurations for a programming structure portion from which a programming structure pattern may be selected.

Mask-programmable ROM cell

A process for efficiently programming a programmable logic device (PLD) is provided. A basis set for a desired matrix of programming pattern ('pattern matrix') is a set of row patterns from which all the row patterns of the pattern matrix can be derived by applying a Boolean operation on two or more row patterns of the basis set. The disclosed process derives a minimal basis set, i.e., a set with the smallest number of row patterns among basis sets for the given pattern matrix.

Process for programming PLDs and embedded non-volatile memories

A method and apparatus for checking the integrity of a device tester used in the manufacture of semiconductor devices. A device tester is used to exercise different aspects of a semiconductor device. The tester is programmed with appropriate control software that fully tests the electrical and functional characteristics of the semiconductor device.

Method and apparatus for checking the integrity of a device

A method and apparatus for testing an integrated circuit device. An integrated circuit device undergoes testing in at least two different stages of the manufacturing process. At one stage, the semiconductor wafer containing multiple chip dice is probed by a probe tester that tests each of the dice individually. At another stage, after an individual chip die has been encapsulated in a package, a package tester tests and exercises the functions of the chip.

Method and apparatus of testing an integrated circuit device

A circuit that provides for digitally programmable high voltage drive, as well as fast current limiting capability for testing of integrated circuits. The circuit also provides for digitally programmable slew rate control for controlling the rise and fall times of an output voltage. Integrated circuits requiring low voltage and high voltage tests at different speeds and with different current limiting conditions, or low and high current forcing with different voltage clamp levels, or a mixture of the two can be tested in a single continuous test pattern using the circuit of the present invention.

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Hillsboro, OR, United States of America

Ernest Allen, Iii