Motorola Corporation

Freescale Semiconductor,inc.

Texas Instruments Corporation

Eric W Tisinger

Jade H Alberkrack

Mark Edward Schlarmann

Ahmed Essam Hashim

Sang Yong Lee

Steven M Barrow

Youhao Xi

Jeff W Hall

David M Okada

Yau Kin Hon

Uzair Mohammed

Mitchell A Belser

A system has an input voltage source, a power stage coupled to the input voltage source, a load coupled to an output node of the power stage and a control circuit, the control circuit implemented on a semiconductor die and including: an error amplifier having a first input, a second input and an output; a voltage divider coupled to the output node and configured to provide an output voltage sense value to the first input of the error amplifier; and a programmable reference voltage circuit with an output coupled to the second input of the error amplifier. The programmable reference voltage circuit includes: a reference voltage source; scaling circuit components between the reference voltage source and the second input of the error amplifier; and a switch between the reference voltage source and the second input of the error amplifier. The control circuit is coupled to the power stage and is configured to generate a control signal for switches of the power stage.

Wide input voltage low IQ switching converter

An SMPS current mode control loop with an adjusted cycle-by-cycle peak current limit for buck and boost (and bidirectional buck/boost) regulators. An SMPS regulator can include a PWM driver to drive switching control signals with a PWM duty cycle to an output terminal OUT, and a PWM controller to control the PWM duty cycle based on a current mode control loop that includes slope compensation to provide a signal VPK corresponding to a current sense signal from a current sense terminal CS, based on sensed peak current through the energy storage element, superimposed with an injected slope compensation current corresponding to a predefined slope compensation based on PWM duty cycle. Adjusted peak limit circuitry generates a signal VLMT corresponding to an adjusted peak current limit based on a pre-defined peak current limit threshold for the energy storage element, including generating a peak limit adjustment current corresponding to the injected slope compensation current, and combining the peak limit adjustment current with the pre-defined peak current limit threshold so that VLMT is substantially constant.

Cycle-by-cycle peak current limiting in current mode buck/boost converters

A microelectromechanical system (MEMS) package is disclosed herein. The MEMS package includes a movable mass. The MEMS package further includes a first and second sense electrodes spaced apart from the movable mass. The first and second sense electrodes are configured to be electrically coupled with a controller. The MEMS package further includes a first test electrode and a second test electrode spaced apart from the movable mass. The first and the second test electrodes are configured to be electrically connected to first and second external electrical connectors, respectively. The first and second test electrodes are biased at a first voltage and a second voltage, respectively, when the first and second external electrical connectors are connected to external voltage sources.

Microelectromechanical system package and method of testing

A comparator has a first input, a second input, an output, a control electrode of a first hysteresis transistor coupled to the output, and a control electrode of a second hysteresis transistor coupled to the output. A method for testing the comparator includes: reconfiguring the comparator to be an amplifier with unity gain feedback; providing an input voltage to the input; providing a first voltage to the first hysteresis transistor to provide a first offset voltage; measuring a first output voltage at the output; removing the first voltage from the first hysteresis transistor; providing the first voltage to the second hysteresis transistor; and measuring a second output voltage at the output.

Comparator circuit with hysteresis, test circuit, and method for testing

A Schmitt trigger circuit having a test circuit and method for testing are provided. The Schmitt trigger test circuit includes switches for reconfiguring the Schmitt trigger for testing by shorting the input and output terminals of an inverter and by opening a feedback path to allow the application of test voltages to the gates of feedback transistors coupled to the inverter. The method includes: directly connecting an input terminal of the inverter to an output terminal of the inverter; providing a first power supply voltage to the feedback transistors coupled to the inverter; measuring a first voltage at the input terminal; removing the first power supply voltage from the feedback transistors; providing a second power supply voltage to the feedback transistors. The test circuit and method reduce the test time by eliminating the need to ramp an input voltage while monitoring the output.

Schmitt trigger with test circuit and method for testing

An integrated power factor control circuit (12) for keeping an average AC line current sinusoidal and in phase with the line voltage. The integrated power factor control circuit (12) provides a boosted DC voltage greater than the amplitude of the line voltage. A transconductance amplifier (16) provides a boosted source and sink current when an output voltage is significantly out of regulation. The boosted source and sink current of the transconductance amplifier (16) increases the speed in which the voltage control loop can react to an output voltage change and reduces the time needed to generate the regulated voltage under startup. A comparator (17) provides a boost current at start up and senses a no-load condition during normal operation. The comparator (17) senses the no-load condition and stops switching to eliminate further output charging before an out of range condition occurs.

Power factor control circuit having a boost current for increasing a

A novel off-line bootstrap startup circuit (10) including a high voltage device (100) for providing an initial bias voltage to an integrated circuit (IC) is provided. The high voltage device includes an NMOS transistor (102) having a high source to ground breakdown voltage thereby extending a bias voltage range provided to the IC. This bias voltage range may be needed to support large comparator (303) hysteresis and allow for an unregulated bias voltage. The bootstrap startup circuit becomes inoperative when the bias voltage exceeds a predetermined value.

Off-line bootstrap startup circuit

A leading edge blanking circuit has been provided. The LEB circuit (20) includes a minimum number of components for monitoring a gate voltage of a transistor (28) and passing a current sense signal, which senses the current level through the transistor, to subsequent control circuitry (32) when the gate voltage exceeds a predetermined threshold (V.sub.LEBTH). Further, the predetermined threshold is chosen to be between the Miller plateau voltage of the transistor and the desired maximum gate voltage.

Leading edge blanking circuit

An output driver stage (10) having current limit protection has been provided. The output driver stage provides current protection for both itself and for an output load which may be coupled to an output terminal (12). The current limit protection is accomplished via a one shot timer (28) which controls the charge at the output terminal. Further, the one shot timer may be activated by a plurality of output stages which respectively control a plurality of output loads.

Output driver stage with two tier current limit protection

A control circuit having slope compensation includes a current reference circuit for providing a reference current at an output. A resistor is coupled to the current reference circuit for varying the reference current. A current mirror circuit has a plurality of outputs, and an input which is coupled to the output of current reference circuit for receiving the reference current. A capacitor is coupled between a first one of the plurality of outputs of the current mirror circuit and a first supply voltage terminal. A charging/discharging circuit is coupled to the capacitor and to a second one of the plurality of outputs of the current mirror circuit for charging the capacitor to a first predetermined voltage at a first rate and discharging the capacitor to a second predetermined voltage at a second rate wherein the signal appearing across the capacitor is a ramp voltage signal. A level shift circuit is coupled to the first one of the plurality of outputs of the current mirror circuit for voltage shifting the ramp voltage signal across the capacitor by a predetermined amount. A multiplier circuit is coupled to the level shift circuit and responsive to the reference current supplied from a third one of the plurality of the outputs of the current mirror circuit for providing a ramp current signal at an output, the peak voltage of the ramp current signal being a function of the value of the resistor wherein the ramp current signal at the output of the multiplier circuit can be utilized to provide slope compensation to a signal supplied at an input of the control circuit.

Slope compensation circuit for stabilizing current mode converters

A power supply monitoring circuit for operating in a plurality of modes comprising first and second single input comparators coupled to first and second inputs, respectively, for sensing the voltage levels thereof. A reference circuit for generating a reference voltage at a first output. A programming circuit coupled to the outputs of the first and second single input comparators and being responsive to a third input for providing the selection of plurality of operation modes and for providing second and third outputs which are function of the voltage levels appearing at the first and second inputs.

Universal power supply monitor circuit

A driver circuit for driving capacitive loads comprises a regenerative high side driver and a low side driver. A boost circuit responsive to an input signal turns the regenerative high side driver on hard producing a very fast output rise time. A feedback circuit is provided which disables the boost circuit when the output voltage reaches a predetermined value conserving supply current. A sustaining resistor provides base current to maintain the high side driver on after the feedback circuit has disabled the boost circuit.

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Chandler, AZ, United States of America

Eric W Tisinger