Globalfoundries Inc.

Globalfoundries U.S. Inc.

Eric S Kozarsky

Jianwei Peng

Hong Yu

Guillaume Bouche

Nicholas V Licausi

George Robert Mulfinger

Man Gu

Shiv Kumar Mishra

Kaustubh Shanbhag

Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

Carbon implantation for thicker gate silicide

The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

Semiconductor structure with shared well

A semiconductor cell includes a substrate and an array of at least five substantially parallel fins having substantially equal fin widths disposed on the substrate. The array includes a predetermined minimum spacing distance between at least one pair of adjacent fins within the array. The array has a first n-type fin for an n-type semiconductor device, and a first p-type fin for a p-type semiconductor device. The first p-type fin is disposed adjacent the first n-type fin and spaced a predetermined first n-to-p distance apart from the first n-type fin. The first n-to-p distance is greater than the minimum spacing distance and less than the sum of the fin width plus twice the minimum spacing distance.

Combined SADP fins for semiconductor devices and methods of making the same

Approaches for providing a fin field effect transistor device (FinFET) with a planar block area to enable variable fin pitch and width are disclosed. Specifically, approaches are provided for forming a plurality of fins patterned from a substrate, the plurality of fins comprising: a first set of fins having a variable pitch and a variable width; and a second set of fins having a variable pitch and a uniform width, wherein the first set of fins is adjacent the second set of fins. In one approach, the first set of fins is patterned from the planar block area, which is formed over the substrate, and the second set of fins is formed using a sidewall image transfer (SIT) process.

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Ballston Spa, NY, United States of America

Eric S Kozarsky