Vanguard International Semiconductor Corporation

Eric S Jeng

Kung Linliu

Hsu-Li Cheng

A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer formed from an organic anti-reflective coating (ARC) material, where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing a reactant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer, where the patterned focusing layer has the reproducible negative etch bias with respect to the patterned photoresist layer. Finally, there is etched through a second etch method the blanket target layer to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer. The patterned target layer has a reproducible second etch bias with respect to the patterned focusing layer, where the reproducible second etch bias does not substantially compensate the reproducible negative etch bias. Through the method, there may be formed patterned layers, such as gate electrodes within field effect transistors (FETs), of linewidth at least as narrow as about 0.25 micron while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation.

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Taipei, Taiwan

Eric S Jeng