Nxp B.v.

Eric Ooms

Xin Lin

Ronghua Zhu

Piet Wessels

Gaurav Singh Bisht

Jayaraj Thillaigovindan

Jerome Dubois

Naveen Agrawal

A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.

Method for making high voltage transistors insensitive to needle defects in shallow trench isolation

A method of manufacturing a semiconductor device includes forming a trench that includes a needle defect, depositing a high density plasma oxide over the trench including the needle defect, removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch, and after the step of applying the oxide etch, etching back the needle defect by applying a polysilicon etch.

Method for reducing defects in shallow trench isolation

Growing community of inventors

San Jose, CA, United States of America

Eric Ooms