Eastman-kodak Company

Truesense Imaging, Inc.

Semiconductor Components Industries, LLC

Omnivision Technologies, Inc.

Eric J Meisenzahl

Shen Wang

Antonio S Ciccarelli

Robert P Fabinski

James E Doran

Greg L Archer

David N Nichols

John Paul McCarten

Laurel J Pace

John P Shepherd

Eric Gordon Stevens

Herbert J Erhardt

Joseph R Summa

Edward T Nelson

Richard B Brolly

Dennis J Vankerkhove

John P Mccarten

Various embodiments of the present technology may comprise methods and apparatus for a CCD image sensor. The image sensor may comprise a center channel disposed along a horizontal center line of the pixel array for collecting and transferring charge. The center channel is electrically coupled to a lateral overflow drain. In various embodiments, the image sensor may comprise a light shield under a gap between neighboring microlenses, such as a gap along the center line, to block light, such as to maintain a uniform, spatial sampling pattern across the device. In various embodiments, the image sensor may comprise a barrier region disposed between the center channel and the lateral overflow drain, for example to prevent charge from the lateral overflow drain being injected back into the center channel and adjacent pixels.

Methods and apparatus for a CCD image sensor

A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.

Methods for producing image sensors having multi-purpose architectures

Methods for producing image sensors having multi-purpose architecture

Multi-purpose architecture for CCD image sensors

In various embodiments, image sensors include an imaging array of optically active pixels, a dark-reference region of optically inactive pixels, and two light shields disposed over the dark-reference region and having openings therein.

Dark reference in CCD image sensors

A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.

Stitching methods using multiple microlithographic expose tools

A method for producing a device in one or more layers of patternable material disposed over a substrate uses multiple exposure tools having different resolution limits and maximum expose field sizes. An abutting field pattern is exposed and stitched in one layer of patternable material using one exposure tool and a first mask. A periphery pattern is then exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The maximum expose field of the first exposure tool is smaller than a size of the device while the maximum expose field of the second exposure tool is at least as large as, or larger, the size of the device so that the combination of the stitched abutting field pattern and the periphery pattern forms a complete pattern in the patternable material.

A charge-coupled device (CCD) image sensor includes a layer of a semiconductor material having a first conductivity type. A horizontal CCD channel region of a second conductivity type is disposed in the layer of the semiconductor material. The horizontal CCD channel region includes multiple phases that are used to shift photo-generated charge through the horizontal CCD channel region. Distinct overflow drain regions are disposed in the layer of semiconducting material, with an overflow drain region electrically connected to only one particular phase of the horizontal CCD channel region. A buffer region of the second conductivity type can be used to electrically connect each overflow drain to the one particular phase of the horizontal CCD channel. Multiple barrier regions are disposed in the layer of semiconductor material, with each barrier region disposed between each overflow drain and the one particular phase electrically connected to the drain.

CCD image sensors having multiple lateral overflow drain regions for a horizontal shift register

A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.

Identification of dies on a semiconductor wafer

An image sensor includes a substrate having a plurality of photosensitive areas, a light shield positioned spanning the photosensitive areas in which light shield a plurality of apertures are formed, and a plurality of microlens each disposed centered on one of the apertures such that a focal point of the incident light through each microlens is substantially extended into the substrate to a point where a portion of the incident light directed onto the periphery of each microlens is blocked by a light shield.

Image sensors with improved angle response

One or more charge storage regions in a charge-coupled device (CCD) shift register can contain residual charge that did not transfer to a reset drain during a reset operation. An image sensor drains the residual charge from each charge storage region by shifting the residual charge to an adjacent charge storage region and resetting the CCD shift register one more time. The process of resetting the CCD shift register, shifting the residual non-image charge to an adjacent charge storage region, and resetting the CCD shift register again can be repeated any number of times.

System and method for draining residual charge from charge-coupled device (CCD) shift registers in image sensors having reset drains

A CCD image sensor comprises photosensitive elements arranged in rows and columns, vertical CCDs each having vertical shift elements associated with respective ones of the photosensitive elements of a corresponding one of the columns, and a horizontal CCD comprising horizontal shift elements. The image sensor further comprises a transition region arranged between the vertical CCDs and the horizontal CCD. The transition region is configured to separate each of a plurality of signal channels provided by respective ones of the vertical CCDs into first and second parallel signal channels and to controllably direct selected ones of the parallel signal channels to the horizontal shift elements of the horizontal CCD in accordance with a designated readout sequence.

Charge-coupled device image sensor with vertical binning of same-color pixels

A charge-coupled device image sensor includes (a) a two-dimensional array of pixels having a plurality of rows and columns, the two-dimensional array includes: (i) a plurality of gates arranged as a charge-coupled device; wherein the array further includes a plurality of charge-coupled devices that are arranged to be clocked by one or more common timing signals; (ii) a transition region, electrically connected to the array, having a first and second row of gates in which the second row is electrically mated into a plurality of first and second pairs of gates in which first pairs of gates are clocked by a first common timing signal and second pairs of gates are clocked by a second common timing signal; wherein the first row of gates are all clocked with a third common timing signal; and (b) a horizontal shift register adjacent the second row of gates for receiving charge from the second row of gates.

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Ontario, NY, United States of America

Eric J Meisenzahl