Lam Research Corporation

Eric D Wagganer

Douglas L Keil

Peter K Loewenhardt

Helen H Zhu

Rao Annapragada

Daniel Le

Bryan A Helmer

Tri Le

Jim Bowers

A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.

Line edge roughness reduction for trench etch

A semiconductor manufacturing process wherein an organic anti-reflective coating (ARC) is plasma etched with selectivity to an underlying dielectric layer and/or overlying photoresist. The etchant gas is fluorine-free and includes a carbon-containing gas such as CO gas, a nitrogen-containing gas such as N , an optional oxygen-containing gas such as O , and an optional inert carrier gas such as Ar. The etch rate of the ARC can be at least 10 times higher than that of the underlying layer. Using a combination of CO and O with N and a carrier gas such as Ar, it is possible to obtain dielectric:ARC selectivity of at least 10. The process is useful for etching contact or via openings in damascene and self-aligned contact or trench structures.

Plasma etching of organic antireflective coating

Methods for etching a trench into a dielectric layer are provided. One exemplary method controls an ion-to-neutral flux ratio during etching so as to achieve a neutral limited regime in an ion assisted etch mechanism where the neutral limited regime causes bottom rounding. The method includes modulating physical sputtering causing microtrenching to offset the bottom rounding so as to produce a substantially flat bottom trench profile. Some notable advantages of the discussed methods of etching a trench into a dielectric layer includes the ability to eliminate the intermediate etch stop layer. Elimination of the etch stop layer will decrease fabrication cost and process time. Additionally, the elimination of the intermediate stop layer will improve device performance.

Profile control of oxide trench features for dual damascene applications

An improved method of forming a metallization layer in a layer stack is disclosed. In one aspect of the invention, a method of performing a lithographic damascene etch on a layer stack to form a metal line is disclosed. The layer stack, which is disposed above a substrate, is comprised of an underlying layer. The method of performing the lithographic damascene etch comprises the steps of depositing a photoresist layer above the layer stack and forming a trench in the photoresist layer so that the trench is positioned over the underlying layer of the layer stack. The method continues with depositing a metal layer over the top surface of the photoresist layer and filling the trench, planarizing the metal layer down to about a level of the top surface of the photoresist layer to define a top surface of a metal line, and removing the photoresist layer to leave gaps around the metal line. A dielectric material is then deposited to fill the gaps around the metal line up to a level of about the top surface of the metal line.

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Milpitas, CA, United States of America

Eric D Wagganer