International Business Machines Corporation

Globalfoundries Inc.

Globalfounries Inc.

Eric D Perfecto

Charles Leon Arvin

Chandrika Prasad

Roy Rongqing Yu

George E White

Harry David Cox

Suryanarayana Kaja

Kimberley A Kelly

Thomas Anthony Wassick

Wolfgang Sauter

Minhua Lu

Krystyna Waleria Semkow

Madhavan Swaminathan

Mukta S Farooq

Ashwani K Malhotra

Bouwe W Leenstra

Keshav B Prasad

Sampath Purushothaman

Jae-Woong Nah

Laertis Economikos

Brian Richard Sundlof

Lewis Sigmund Goldmann

Brian Michael Erwin

Ajay Prabhakar Giri

Gordon J Robbins

Charles C Goldsmith

Mukta G Farooq

Katsuyuki Sakuma

Kamalesh K Srivastava

Michael F McAllister

Patrick William Dehaven

Julien Sylvestre

William Harrington Brearley

Arthur Gilman Merryman

Renee L Weisman

Paul F Findeis

James Patrick Wood

Voya Rista Markovich

Timothy Harrison Daubenspeck

Gareth Geoffrey Hougham

Hilton T Toy

Benjamin V Fasano

Sudipta Kumar Ray

Claudius Feger

Peter Jeffrey Brofman

Tien-Jen Cheng

Raed A Sherif

Richard Francis Indyk

Donald W Henderson

Daniel George Berger

Giulio DiGiacomo

Srinivasa S N Reddy

Hsichang Liu

William Frederick Shutler

Mark Harrison McLeod

Joseph Michael Sullivan

Jennifer D Schuler

John R Pennacchia

James A McDonald

Michael S Cranmer

Jeffrey P Gambino

John Ulrich Knickerbocker

Christopher David Muzzy

Marie Angelopoulos

Thomas J Brunschwiler

David John Russell

Jon Alfred Casey

Donald Francis Canaperi

Willi Volksen

David L Questad

James A Busby

Kwong Hon Wong

Sung Kwon Kang

Michael P Belyansky

Spyridon Skordas

James John Kelly

Raymond R Horton

Qianwen Chen

Ian D Melville

Thomas J Fleischman

Nicholas A Polomoff

Rajneesh Kumar

Sally Ann Swanson

Shahid Ahmad Butt

Leena Paivikki Buchwalter

Ekta Misra

Ananda H Kumar

Michael Berger

Umar M Ahmad

James Anthony Tornello

Dale Curtis McHerron

Jeffrey W Labadie

Valerie A Oberson

Karen P McLaughlin

Koushik Ramachandran

Srinivasa N Reddy

Balaram Ghosal

Jorge A Lubguban

Vivek M Sura

Martha Inez Sanchez

A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Resist patterned redistribution wiring on copper polyimide via layer

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Infrared debond damage mitigation by copper fill pattern

A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.

Chip-to-chip and chip-to-substrate interconnections in multi-chip semiconductor devices

Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e., when the first electrode is removed from the plating solution), wherein the second electrode and the third electrode have opposite polarities that switch at regular, relatively fast, intervals, thereby limiting degradation of the second electrode and/or the plating solution.

Electrodeposition systems and methods that minimize anode and/or plating solution degradation

A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

Structure for establishing interconnects in packages using thin interposers

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Semiconductor device contact structure having stacked nickel, copper, and tin layers

A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

Non-transparent microelectronic grade glass as a substrate, temporary carrier or wafer

A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

Method for establishing interconnects in packages using thin interposers

A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal.

Silver alloying post-chip join

Multilayered contact structure having nickel, copper, and nickel-iron layers

Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Electromigration-resistant lead-free solder interconnect structures

Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.

Universal solder joints for 3D packaging

A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.

Use of electrolytic plating to control solder wetting

The present invention relates generally to and more particularly, to a method of fabricating a pillar interconnect structure with non-wettable sidewalls and the resulting structure. More specifically, the present invention may include exposing only the sidewalls of a pillar to an organic material that reacts with metal of the pillar to form an organo-metallic layer on sidewalls of the pillar. The organo-metallic layer may prevent solder from wetting on the sidewalls of the pillar during subsequent bonding/reflow processes.

Organic coating to inhibit solder wetting on pillar sidewalls

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Poughkeepsie, NY, United States of America

Eric D Perfecto