Densbits Technologies Ltd.

Amazon Technologies, Inc.

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Erez Sabbag

Hanan Weingarten

Avi Steiner

Avigdor Segal

Michael Katz

Ilan Bar

Eli Sterin

Itai Avron

Ofir Avraham Kanter

Ron Diamant

Erez Izenberg

Adi Habusha

Leonid Baryudin

Barak Wasserstrom

Amir Nassie

Anna Rom-Saksonov

Noga Smith

Se Wang Oh

Evgeni Pinkovich

A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.

Correcting memory data using an error code and a memory test result

Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.

Memory extension with error correction

Execution flows of a program can be characterized by a series of execution events. The rates at which these execution events occur for a particular program can be collected periodically, and the execution events statistics can be utilized for both training a machine learning model, and later on for making classification inferences to determine whether a program run contains any abnormality. When an abnormality is encountered, an alert can be generated and provided to supervisory logic of a computing system to indicate that an abnormal program flow has been detected.

Program flow classification

The integrity of transmitted data can be protected by causing that data to be transmitted twice, and calculating protection information (PI) for the data from each transmission. The PI can include information such as a checksum or signature that should have the same value if the data from each transmission is the same. If the PI values are not the same, an error handling procedure can be activated, such as may retry the transmission. For write operations, the data can be transmitted twice from a source to a storage destination, while for read operations, the data can be transmitted to a recipient then sent back from the recipient to the storage device, with PI calculated for each transmission. A component such as a storage processor can perform at least this comparison step. Such approaches can also be used for network transmission or high performance computing.

Data integrity protection

Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.

Selective erasure decoding for memory devices

An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.

System and method for encoding using multiple linear feedback shift registers

A computer readable medium, a system and a method for flash memory device that my store instructions for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device, receiving, from the host computer, a second command that is indicative of a manner in which at least one entity out of (a) memory management metadata, (b) the first data unit and (c) at least one other data unit, should be stored in the flash memory device, and programming the at least one entity in the flash memory device in response to the second command.

Method and system for split flash memory management between host and storage controller

A method for memory management, the method may include calculating, by a memory controller, an estimate of an effect of read operations on a first flash memory entity; and performing, by the memory controller, at least one memory management operation in response to the estimate of the effect of read operations on the first flash memory entity.

Management of memory units

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.

Flash memory chip processing

A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.

Digital signaling processing for three dimensional flash memory arrays

A method for wear reduction of a flash memory module, the method may include reading data stored in a group of flash memory cells to provide a read data; wherein the reading comprise supplying a bias voltage that is lower than a write bias voltage; wherein the write bias voltage was supplied to the group of flash memory cells during a writing of the data to the group of flash memory cells; and decoding the read data, by applying a decoding process of a given complexity, to provide decoded data.

Flash memory cells wear reduction

A non-transitory computer readable medium that stores instructions for: reading a first group of flash memory cells using a reference read threshold to obtain multiple read results; processing the multiple read results by performing at least one out of calculating a distribution of values of the multiple read results and counting a number of read results of a certain value; estimating at least one actual read threshold to be used during future read attempts in response to at least one out of (i) the number of read results of the certain value and (ii) distribution information about a distribution of values of the read results; and reading a second group of flash memory cells using the at least one actual read threshold to provide actual read results.

Read threshold determination using reference read threshold

Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device.

Method, system and computer readable medium for copy back

A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory controller that may be configured to determine a bit significance level of the nonvolatile memory block; program the nonvolatile memory block by performing at least one programming phase; and program the nonvolatile memory block to an erase value that may be higher than the pre-erase value; wherein the erase value and the pre-erase value may be selected based on the bit significance level of the nonvolatile memory block. The method may include packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block in order of the three SLC bit significances.

Device, system, and method for reducing program/read disturb in flash arrays

A system, a method and a non-transitory computer readable medium for generating soft information. The method may include performing a first set of read attempts of flash memory cells using a first set of read thresholds to provide first read results; calculating for each flash memory cell in response to the first read results, first cell information indicative of a first change-inducing read threshold; performing a second set of read attempts of the flash memory cells using a second set of read thresholds to provide second read results, calculating for each flash memory cell in response to the second read results, second cell information indicative of a second change-inducing read threshold; and generating, for each flash memory cell soft information in response to the first cell information and the second cell information of the flash memory cell.

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Kiryat Tivon, Israel

Erez Sabbag