Infineon Technologies Ag

International Business Machines Corporation

Globalfoundries Inc.

Other

Infineon Technologies North America Corp.

United Microelectronics Co.

Erdem Kaltalioglu

Ping-Chuan Wang

Ronald G Filippi

Lijuan Zhang

Hans-Joachim Barth

Mark Hoinkis

Andy Cowley

Timothy Joseph Dalton

Gerald R Friese

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Andrew Tae Kim

Jochen Schacht

Petra Felsner

Chih-Chao Yang

Andrew Herbert Simon

John Anthony Fitzsimmons

Thomas Goebel

Lawrence Alfred Clevenger

Vincent James McGahay

Hermann Wendt

Philipp Riess

Michael Beck

Andrew P Cowley

Markus Naujok

Steffen K Kaldor

Wai-Kin Li

Matthias Hierlemann

Sun-Oo Kim

Cathryn Jeanne Christiansen

Ronald Gene Filippi, Jr

Michael Stetter

Anthony K Stamper

Clement Hsingjen Wann

Yun Yu Wang

Mukta G Farooq

Soon-Cheon Seo

Chengwen Pei

Helmut Horst Tews

Tze-Chiang Chen

Terry Allen Spooner

Yun-Yu Wang

Naftali Eliahu Lustig

Wei Lin

Shahab Siddiqui

Spyridon Skordas

Terence Lawrence Kane

Peter Baumgartner

Kevin R Winstel

Atsushi Ogino

Brett H Engel

Larry Clevenger

Zhuojie Wu

Klaus Herold

Alexander Von Glasow

Thomas Schafbauer

Thomas Benetik

Erwin Ruderer

Ann H McDonald

Peter A Emmi

Uwe Kerst

Dennis J Warner

Naftall E Lustig

Hsueh-Chung Chen

Bucknell Chapman Webb

Griselda Bonilla

Thomas M Shaw

Xiao Hu Liu

Junjing Bao

Eric D Hunt-Schroeder

Samuel S Choi

Tong-Yu Chen

Darryl D Restaino

Nicholas A Polomoff

Gwo-Shii Yang

Moosung Chae

Pak Leung

Chiung-Sheng Hsiung

Yi-Hsiung Lin

Muhammed Shafi Pallachalil

Sunoo Kim

Delores A Bennett

Hans-Joachin Barth

Christian Pils

Chih-Chih Liu

Vincent Mcgahay

Brett H c/o Ibm United Kingdom Ltd Ip Engel

Ann c/o Ibm United Kingdom Ltd Ip Law Mcdonald

An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

IC structure with interdigitated conductive elements between metal guard structures

Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

Interconnect structure having power rail structure and related method

The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

Mechanically anchored C4 pad and method of forming same

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Wafer rigidity with reinforcement structure

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Wafer reinforcement to reduce wafer curvature

Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

Interconnect structures for a security application

A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.

IC structure integrity sensor having interdigitated conductive elements

Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.

Interconnect structures with variable dopant levels

A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

TSV deep trench capacitor and anti-fuse structure

Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

Strain detection structures for bonded wafers and chips

A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Selective local metal cap layer formation for improved electromigration behavior

A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology.

Structures and methods for determining TDDB reliability at reduced spacings using the structures

Growing community of inventors

Newburgh, NY, United States of America

Erdem Kaltalioglu