Micron Technology Incorporated

Applied Materials, Inc.

Sandisk 3d LLC

Round Rock Research, LLC

Conversant Intellectual Property Management Incorporated

Micro Technology, Inc.

Er-Xuan Ping

Lingyi A Zheng

Trung Tri Doan

Lyle D Breiner

Shenlin Chen

Fernando N Gonzalez

Randhir P Thakur

Ronald Allen Weimer

Cem Basceri

Yongjun Jeff Hu

Kevin L Beaman

David J Kubista

Michael L Nuttall

Huiwen Xu

Thomas Jongwan Kwon

Li Li

Randhir P S Thakur

Chih-Chen Cho

Guy T Blalock

Roger R Lee

Tanmay Kumar

D Mark Durcan

Zhiping Yin

Garry Anthony Mercaldi

Behnam Moradi

Jaesoo Ahn

Xiying Chen

Jingyan Zhang

Ying Huang

John Packard

Seiichi Takedai

Roy E Scheuerlein

Xianmin Tang

Kaushal Kishore Singh

Junting Liu

Ludovic Godet

Srinivas D Nemani

Abhijit Basu Mallick

Ellie Y Yieh

Scott Jeffrey DeBoer

Deenesh Padhi

Pai-Hung Pan

Rui Cheng

Zhongze Wang

April Dawn Schricker

Xinhai Han

Husam N Al-Shareef

Jeffrey A McKee

Xiying Costa

Tae Hong Ha

Demetrius Sarigiannis

Sang-Hyeob Lee

Srinivas Guggilla

Gary E Dickerson

Mathew Abraham

Jin Hee Park

Aneesh Nainani

Chorng-Ping Chang

Sree Rangasai Kesapragada

Chin-Chen Cho

Deepak Chandra Sekar

James K Kai

Peter Rabkin

George Matamis

George Samachisa

Schubert S Chu

Henry Chien

Vinod Robert Purayath

Fred D Fishburn

Casey R Kurth

Takashi Whitney Orimoto

Franz Kreupl

Yung-Tin Chen

Hongmei Wang

Wipul Jayasekara

Alper Ilkbahar

Bing K Yen

Yi Zheng

Vijay Parihar

Steven Patrick Maxwell

Abhijit Bandyopadhyay

Sundar Ramamurthy

Eric Blomiley

Ashish Goel

Saurabh Chopra

Chuanbin Pan

Ashutosh Agarwal

Bingxi Sun Wood

Brent A McClure

Kai Ma

Kun Hou

Li Xiao

Minrui Yu

Chu-Chen Fu

Deepak Jadhav

Yoshihide Senzaki

Judon Tony Pan

Dat Nguyen

John Zhang

Debra K Gould

A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800 degrees Celsius, forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.

Methods for silicon carbide gate formation

Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Multi-layer stacks for 3D NAND extendability

Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.

Method and system for three-dimensional (3D) structure fill

The present disclosure provides a film stack structure formed on a substrate and methods for forming the film stack structure on the substrate. In one embodiment, the method for forming a film stack structure on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate and depositing a metal layer on the first adhesion layer, wherein the first adhesion layer and the metal layer form a stress neutral structure.

PVD deposition and anneal of multi-layer metal-dielectric film

Methods and apparatus for depositing a cobalt layer in a feature, such as, a word line formed in a substrate, are provided herein. In some embodiments, method of processing a substrate includes: exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing.

Method and apparatus for depositing cobalt in a feature

Multi-layer stacks for 3D NAND extendibility

A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560&#xb0; C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.

Self-aligned nanodots for 3D NAND flash memory

Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

Hybrid carbon hardmask for lateral hardmask recess reduction

Embodiments described herein provide a remote plasma system utilizing a microwave source. Additionally, generation and deposition techniques for 2D transition metal chalcogenides with large area uniformity utilizing microwave assisted generation of radicals is disclosed. Plasma may be generated remotely utilizing the microwave source. A processing platform configured to deposit 2D transition metal chalcogenides is also disclosed.

Method and apparatus for microwave assisted chalcogen radicals generation for 2-D materials

Embodiments described herein generally relate to methods for forming silicide materials. Silicide materials formed according to the embodiments described herein may be utilized as contact and/or interconnect structures and may provide advantages over conventional silicide formation methods. In one embodiment, a one or more transition metal and aluminum layers may be deposited on a silicon containing substrate and a transition metal layer may be deposited on the one or more transition metal and aluminum layers. An annealing process may be performed to form a metal silicide material.

Methods for forming low resistivity interconnects

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.

Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain

Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate.

Methods of doping substrates with ALD

Growing community of inventors

Meridian, ID, United States of America

Er-Xuan Ping