Tower Semiconductor Ltd.

Ephie Koltin

Yacov Malinovich

David Cohen

Amit Shacham

Yossi Netzer

Israel Rotstein

Margalit Ilovich Ayelet

A method for stitching a plurality of mask regions including the steps of (1) defining cut regions on the mask regions, wherein the cut regions adjoin the edges of the mask regions to be stitched, (2) implementing a first set of design rules in the cut regions, and (3) implementing a second set of design rules outside of the cut regions. The mask regions can be formed on a single reticle or on a plurality of separate reticles. In one embodiment, the first set of design rules specifies that trace patterns in the cut regions have widths greater than trace patterns outside of the cut regions. In another embodiment, the first set of design rules specifies that trace patterns in the cut regions have a minimum spacing greater than trace patterns outside of the cut regions. In yet another embodiment, the first set of design rules specifies that trace patterns can be formed entirely within the cut regions. The stitching method can also include the steps of (1) defining a cut line on a wafer, (2) aligning first and second mask regions with the cut line such that transparent regions of the first and second mask regions have a controlled amount of overlap with respect to the cut line, and (3) selecting the controlled amount of overlap such that a pattern formed by the first and second mask regions has a uniform width adjacent to the cut line.

Stitching design rules for forming interconnect layers

A method for forming a CMOS image sensor cell such that stress is minimized in regions surrounding the light sensitive (e.g., photodiode) portion of the cell, thereby reducing leakage current and minimizing white spots in CMOS image sensors. The field oxide surrounding the light sensitive region is formed with interior angles greater than 90&deg; and/or is continuously curved. The reset gate is offset from the light sensitive regions of active pixel cells by a distance greater than 0.25 &mgr;m. A mask is used during n&plus; doping of the light sensitive region to shield an inner edge of the surrounding field oxide and extends 0.5 &mgr;m or more over the light sensitive region. A mask is provided over the interface between the field oxide and the light sensitive region during sidewall spacer formation. A metal structure contacting the light sensitive region is spaced 0.4 &mgr;m or greater from the surrounding field oxide. Metal lines passing between the light sensitive regions are provided with stress-relieving slits. Metal lines of a guard ring surrounding the pixel array are non-continuous to also provide stress relief.

Method and structure for minimizing white spots in CMOS image sensors

A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate.

Backside illuminated image sensor

Method for making backside illuminated image sensor

Growing community of inventors

Givat Elah, Israel

Ephie Koltin