Samsung Electronics Co., Ltd.

Eon-Soo Jang

Jae-Choon Kim

Mi-Na Choi

Hee-jung Hwang

Young-Deuk Kim

Byeong-Yeon Cho

Hyon-Chol Kim

Eun-Hee Jung

In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

Stack package and method of manufacturing the stack package

A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

Package substrate and semiconductor package including the same

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Yongin-si, South Korea

Eon-Soo Jang