Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

National University of Singapore

Eng Hua Lim

Soh Yun Siah

Chong Wee Lim

Jia Zhen Zheng

Kong Hean Lee

Mei Sheng Zhou

Elgin Kiok Quek

Chew Hoe Ang

Daniel Yen

Chun Hui Low

Randall Cha

Wenhe Lin

Victor Chan

Khee Yong Lim

Chung Woh Lai

Chew-Hoe Ang

Pei Ching Lee

Arthur Ang

Jamin F Fen

Haining S Yang

Simon Yew-Meng Chooi

Liang Choo Hsia

Yelehanka Ramachandramurthy Pradeep

Mei-Sheng Zhou

Kin Leong Pey

Randall Cher Liang Cha

Bei Chao Zhang

Charles Lin

Zheng Zou

Kin-Leong Pey

Peter Chew

Chiew Wah Yap

Beichao Zhang

Jia-Zhen Zheng

Harianto Wong

Kong-Hean Lee

Hai Jiang Peng

Manni Lal

Nguyen Lac

A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Double anneal with improved reliability for dual contact etch stop liner scheme

A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.

Method and structure for forming strained devices

A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width &ldquo;L&rdquo;. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width &ldquo;1&rdquo;. The re-flowed first opening lower width &ldquo;1&rdquo; being less than the pre-reflowed first opening width &ldquo;L&rdquo;. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width &ldquo;1&rdquo;. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

Method to pattern small features by using a re-flowable hard mask

A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.

Method of forming a high performance and low cost CMOS device

A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.

Method for forming L-shaped spacers with precise width control

A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

Method to fabricate a single gate with dual work-functions

A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Method of cobalt silicidation using an oxide-Titanium interlayer

A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

Method of fabricating variable length vertical transistors

Method of forming almost L-shaped spacer for improved ILD gap fill

A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers

A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.

Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate

A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability. The titanium layer is removed to complete formation of a thermally stable cobalt disilicide film in the manufacture of an integrated circuit.

Thermal stability improvement of CoSi2 film by stuffing in titanium

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or &ldquo;unframed&rdquo; electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts

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Singapore, Singapore

Eng Hua Lim